公开(公告)号：US5289344A

公开(公告)日：1994-02-22

申请号：US958496

申请日：1992-10-08

申请人： Jay J. Gagnon ,  Paul J. Panaccione

发明人： Jay J. Gagnon ,  Paul J. Panaccione

IPC分类号： H01L23/495 ,  H05K7/20

CPC分类号： H01L24/48 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49112 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181

摘要： The lead-frame in an integrated circuit package, a standard package designated SOT-89, has a plurality of leads of which at least one is an extension of a die-attach pad. At least one ground wing is formed as an extension of a peripheral portion of the die-attach pad and extends upward to approximately the plane of the top of the die. The ground wing has an upstanding portion and a horizontal portion that are at an angle to each other so as to lock the distal end of the wing in the body of encapsulating resin. An integrated circuit die having at least one electrical connection which is grounded electrically via a terminal and wire bonded to the distal part of the ground wing. A contact surface near the distal end of wing is positioned approximately in the plane of the top of the die. This ground circuit can parallel and can be redundant to a ground circuit through the die via the conductive bond that attaches the bottom of the die to the die-attach pad. The ground lead that is an extension of the die-attach pad serves both to remove heat from the die and to provide an electrical ground connection. The contact surface of the wing provides a point of ground-wire attachment that does not move relative to the encapsulating resin as do other peripheral parts of the die attach pad during temperature cycling and mechanical stress. Thus, a common failure mode, which is called heal-cracking, is substantially eliminated.

摘要翻译： 集成电路封装中的引线框，标为SOT-89的封装，具有多个引线，其中至少一个是管芯安装焊盘的延伸部。 至少一个地面翼片形成为模具附接垫的周边部分的延伸部，并且向上延伸到模具的顶部的大致平面。 地面翼具有彼此成一定角度的直立部分和水平部分，以便将翼片的远端锁定在密封树脂的主体中。 一种具有至少一个电连接的集成电路管芯，该电连接件通过端子和电线接合并接合到接地翼的远端部分。 翼的远端​​附近的接触表面大致位于模具顶部的平面内。 该接地电路可以并联并且可以通过将管芯底部附接到管芯附接焊盘的导电接合通过管芯对接地电路进行冗余。 作为芯片附着焊盘延伸的接地引线用于从模具移除热量并提供电接地连接。 机翼的接触表面提供了在温度循环和机械应力期间，与芯片附接垫的其它外围部分一样，相对于密封树脂不会移动的接地线附接点。 因此，基本上消除了称为愈合裂纹的常见故障模式。

公开(公告)号：US07251872B2

公开(公告)日：2007-08-07

申请号：US10918911

申请日：2004-08-16

申请人： Elie Awad ,  Paul J. Panaccione

发明人： Elie Awad ,  Paul J. Panaccione

IPC分类号： H01R43/00 ,  H01L23/495 ,  H01L21/00

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

摘要翻译： 形成具有引线阵列的芯片封装，其中连续引线相对于彼此在所有三维（X，Y和Z）中交错排列，以允许在密闭空间中可用的大量引线，同时保持最小间隔 相邻引线之间必需。 通过在引线框架上放置不对称的顶部和底部掩模并且部分地蚀刻引线框架的顶部，同时部分地并且在其上蚀刻引线框架的底部来形成引线。 虽然所得到的引线在三维方面是交错的，但是除了用于制造常规封装之外，不需要额外的处理步骤。

公开(公告)号：US06815806B1

公开(公告)日：2004-11-09

申请号：US10623090

申请日：2003-07-17

申请人： Elie Awad ,  Paul J. Panaccione

发明人： Elie Awad ,  Paul J. Panaccione

IPC分类号： H01L23495

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggering in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

摘要翻译： 具有引线阵列的芯片封装，其中连续引线相对于彼此在所有三维（X，Y和Z）中交错。 这种交错布置允许在密闭空间中可用的大量引线，同时保持相邻引线之间所需的最小间隔。 通过在引线框架上放置不对称的顶部和底部掩模并且部分地蚀刻引线框架的顶部，同时部分地并且在其上蚀刻引线框架的底部来形成引线。 虽然所得到的引线在三维方面是交错的，但是除了用于制造常规封装的那些之外，不需要额外的处理步骤。