公开(公告)号：US20180019181A1

公开(公告)日：2018-01-18

申请号：US15456755

申请日：2017-03-13

申请人： Mitsubishi Electric Corporation

发明人： Yasuo KONISHI

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/49

CPC分类号： H01L23/3675 ,  H01L23/053 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49 ,  H01L24/48 ,  H01L2224/49433 ,  H01L2924/19107

摘要： Provided is a technique for enhancing heat dissipation properties in dissipating heat generated in an electrode to a heatsink without impairing bonding properties between the electrode and a wire. In a semiconductor device, a portion of an electrode within an inner region defined by a case, at one surface, i.e., the lower surface with respect to a position in which a wire is connected, a resin portion is provided, the resin portion extending from an inner wall of the case to an upper-surface side of the heatsink. Additionally, in the portion of the electrode within the inner region defined by the case, at one surface, i.e., the lower surface with respect to a position in which the wire is not connected, a thermal conductor is provided, the thermal conductor having higher heat conductivity than the resin portion.

公开(公告)号：US09842792B2

公开(公告)日：2017-12-12

申请号：US15007607

申请日：2016-01-27

申请人： UNITED TEST AND ASSEMBLY CENTER LTD.

发明人： Danny Retuta ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Mary Annie Cheong

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49506 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

公开(公告)号：US09773766B2

公开(公告)日：2017-09-26

申请号：US14422152

申请日：2013-01-09

申请人： SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD. ,  SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.

发明人： Ning Ye ,  Chin-Tien Chiu ,  Suresh Upadhyayula ,  Peng Fu ,  Zhong Lu ,  Cheeman Yu ,  Yuang Zhang ,  Li Wang ,  Pradeep Kumar Rai ,  Weili Wang ,  Enyong Tai ,  King Hoo Ong ,  Kim Lee Bock

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/14 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/18 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/00 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83986 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/143 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

公开(公告)号：US09590529B2

公开(公告)日：2017-03-07

申请号：US14422371

申请日：2012-09-28

申请人： Hitachi, Ltd.

发明人： Satoru Akiyama

IPC分类号： H02H7/122 ,  H02M7/537 ,  H02M1/088 ,  H02M3/156 ,  H02M7/5387 ,  H01L25/00 ,  H03K17/082 ,  H03K17/16 ,  H01L23/495 ,  H02M1/00 ,  H01L23/00

CPC分类号： H02M7/537 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/00 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M1/088 ,  H02M3/156 ,  H02M7/5387 ,  H02M2001/0009 ,  H02M2001/0054 ,  H03K17/0822 ,  H03K17/165 ,  Y02B70/1491 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： An uneven return current is prevented and increase in a loss is suppressed in a power conversion apparatus at the time of inverter operation. The invention includes first and second transistor switch groups in each of which arms are connected in parallel, and sense resistors for detecting a drain current are connected to the first and second transistor switch groups, and a first drive circuit group and the second drive circuit group include means for monitoring a sense current flowing through the sense resistors and a plurality of delay circuits. Further, rising of the plurality of transistor switch groups is controlled by controlling activation and non-activation of the plurality of delay circuits on the basis of a magnitude of the sense current.

摘要翻译： 在逆变器运转时，电力转换装置防止不均匀的回流电流，并且抑制了损耗的增加。 本发明包括并联连接臂的第一和第二晶体管开关组，并且用于检测漏极电流的检测电阻连接到第一和第二晶体管开关组，第一驱动电路组和第二驱动电路组 包括用于监测流过检测电阻器的感测电流和多个延迟电路的装置。 此外，通过基于感测电流的大小来控制多个延迟电路的激活和非激活来控制多个晶体管开关组的上升。

公开(公告)号：US09461002B2

公开(公告)日：2016-10-04

申请号：US14874189

申请日：2015-10-02

申请人： NXP B.V.

发明人： Jeroen Antoon Croon ,  Coenraad Cornelis Tak

IPC分类号： H01L29/15 ,  H01L23/552 ,  H01L23/498 ,  H01L29/872 ,  H01L21/48 ,  H01L29/205 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/205 ,  H01L29/872 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/12032 ,  H01L2924/15313 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/07802 ,  H01L2924/00

摘要： A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device. Both the cathode and the first electrically conductive portion of the carrier are electrically isolated from a backside of the semiconductor substrate.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括安装在载体上的半导体衬底。 半导体衬底包括肖特基二极管。 肖特基二极管具有阳极和阴极。 半导体器件还包括将阴极连接到载体的第一导电部分的一个或多个接合线。 半导体器件还包括将阳极连接到载体的第二导电部分的一个或多个接合线。 载体的第一导电部分与载体的第二导电部分电隔离。 载体的第一导电部分被配置为在装置的操作期间提供防止与阳极切换相关的电磁干扰的屏蔽。 载体的阴极和第一导电部分都与半导体衬底的背面电绝缘。

公开(公告)号：US20160260691A1

公开(公告)日：2016-09-08

申请号：US14912547

申请日：2014-08-27

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Masaki AOSHIMA

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L27/082

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49805 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0823 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81424 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor module includes: a first semiconductor chip including a surface provided with a first signal electrode; a second semiconductor chip arranged apart from the first semiconductor chip and including a surface on the first semiconductor chip side provided with a second signal electrode; a first signal lead electrically connected to the first signal electrode; and a second signal lead electrically connected to the second signal electrode. The first signal lead and the second signal lead are arranged so that a height position of the first signal lead and a height position of the second signal lead match in a height direction that is toward the second semiconductor chip from the first semiconductor chip.

摘要翻译： 半导体模块包括：第一半导体芯片，包括设置有第一信号电极的表面; 第二半导体芯片，与第一半导体芯片分开设置并且包括在设置有第二信号电极的第一半导体芯片侧上的表面; 电连接到第一信号电极的第一信号引线; 以及电连接到第二信号电极的第二信号引线。 第一信号引线和第二信号引线被布置成使得第一信号引线的高度位置和第二信号引线的高度位置在从第一半导体芯片朝向第二半导体芯片的高度方向上匹配。

公开(公告)号：US20160007959A1

公开(公告)日：2016-01-14

申请号：US14728341

申请日：2015-06-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungchan KANG ,  Byunggil JEONG ,  Sangha PARK ,  Hyungjae SHIN

IPC分类号： A61B8/00

CPC分类号： A61B8/4444 ,  A61B2562/166 ,  B06B1/0292 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Provided are capacitive micromachined ultrasonic transducer (CMUT) probes that use wire bonding. A CMUT probe includes a CMUT chip which includes a plurality of first electrode pads which are disposed on a first surface thereof, a printed circuit board (PCB) which is disposed on the first surface of the CMUT chip and which is configured to expose the plurality of first electrode pads, a plurality of second electrode pads which are disposed on the PCB and which correspond to respective ones of the plurality of first electrode pads, and a plurality of wires which connect each respective one of the plurality of first electrode pads to the corresponding one of the plurality of second electrode pads.

摘要翻译： 提供使用引线接合的电容微加工超声波换能器（CMUT）探针。 CMUT探针包括CMUT芯片，其包括设置在其第一表面上的多个第一电极焊盘，布置在CMUT芯片的第一表面上的印刷电路板（PCB），其被配置为暴露多个 的第一电极焊盘，多个第二电极焊盘，其布置在PCB上并且对应于多个第一电极焊盘中的相应电极焊盘，以及多个电线，其将多个第一电极焊盘中的每一个连接到 对应的多个第二电极焊盘之一。

公开(公告)号：US20150371950A1

公开(公告)日：2015-12-24

申请号：US14732491

申请日：2015-06-05

申请人： Renesas Electronics Corporation

发明人： Masafumi TOMODA ,  Masayuki TSUKUDA

IPC分类号： H01L23/528 ,  H01L23/58 ,  H01L23/50

CPC分类号： H01L23/5286 ,  H01L23/50 ,  H01L23/5386 ,  H01L23/58 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device includes a multilayer interconnect layer formed over a substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column including a first I/O cell, first and second inner peripheral cell columns formed at an inner peripheral side of the outer peripheral cell column, the first and second inner peripheral cell columns including a second I/O cell, and signal interconnects for forming an internal circuit of the semiconductor device, arranged between the first inner peripheral cell column and the second inner peripheral cell column.

摘要翻译： 半导体器件包括在衬底上形成的多层互连层，在平面图中沿着衬底的边缘设置的外周单元列，外周单元列包括第一I / O单元，第一和第二内周单元列 形成在外周单元列的内周侧，第一和第二内周单元列包括第二I / O单元和用于形成半导体器件的内部电路的信号互连，布置在第一内周单元列 和第二内周细胞柱。

公开(公告)号：US09184151B2

公开(公告)日：2015-11-10

申请号：US13046433

申请日：2011-03-11

申请人： Ng Kok Siang ,  Wong Wai Loon

发明人： Ng Kok Siang ,  Wong Wai Loon

IPC分类号： H01L21/44 ,  H01L23/488 ,  H01L23/00

CPC分类号： H01L24/85 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A method and apparatus for mixed wire bonding and staggered bonding pad placement. A first plurality of bonding pads is arranged on a semiconductor device. A second plurality of bonding pads is also arranged on the semiconductor device. The bonding pads of the second plurality of bonding pads are arranged in a staggered pattern, such that the first and second pluralities of bonding pads form one of a plurality of double rows of bonding pads on the semiconductor device.

摘要翻译： 一种用于混合引线键合和交错键合焊盘放置的方法和装置。 在半导体器件上布置有第一多个接合焊盘。 第二多个接合焊盘也布置在半导体器件上。 第二多个接合焊盘的接合焊盘以交错图案布置，使得第一和第二多个接合焊盘在半导体器件上形成多个双排接合焊盘中的一个。

公开(公告)号：US20150228563A1

公开(公告)日：2015-08-13

申请号：US14691690

申请日：2015-04-21

申请人： Texas Instruments Incorporated

发明人： Lee Han Meng@ Eugene Lee ,  Sueann Lim Wei Fen ,  Sarel Bin Ismail

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L21/4821 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5328 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83862 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00

摘要： A lead frame device may include an integral die pad member, two separate finger members, a central body portion, each of the finger members have a top and a bottom surface connected by a peripheral edge surface. The lead frame also has a first ear portion, and a second ear portion, each has an ear top surface and an ear bottom surface coplanar with the top surface and bottom surface of the central body portion. The lead frame also has a first longitudinally extending groove and second longitudinally extending groove separate the first ear portion and the second ear portion from the central portion. The first ear portion and the second ear portion each have an abutment surface.

摘要翻译： 引线框架装置可以包括整体的管芯焊盘部件，两个单独的指状部件，中心主体部分，每个指状部件具有通过周边边缘表面连接的顶部和底部表面。 引线框架还具有第一耳部和第二耳部，每个耳部具有与中心主体部分的顶表面和底表面共面的耳顶表面和耳底表面。 引线框架还具有第一纵向延伸的凹槽和第二纵向延伸凹槽，其将第一耳部和第二耳部从中心部分分开。 第一耳部和第二耳部各自具有邻接表面。