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    Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller
    2.
    发明授权
    Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller 有权
    用于对DMA控制器进行编程的程序和设备，其中翻译的物理地址存储在地址处理单元的缓冲寄存器中，然后施加到数据总线并存储在DMA控制器的寄存器中

    公开(公告)号：US07581039B2

    公开(公告)日：2009-08-25

    申请号：US11179033

    申请日：2005-07-11

    申请人： Albert Martinez ,  Jean Nicolai

    发明人： Albert Martinez ,  Jean Nicolai

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F12/1081

    摘要： A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

    摘要翻译： 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

    Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers
    3.
    发明授权
    Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers 有权
    用于在芯片上的系统中对DMA控制器进行编程的方法和系统，其中DMA控制器具有源，目的地和大小寄存器

    公开(公告)号：US07467239B2

    公开(公告)日：2008-12-16

    申请号：US11185529

    申请日：2005-07-20

    申请人： Jean Nicolai ,  Albert Martinez

    发明人： Jean Nicolai ,  Albert Martinez

    IPC分类号： G06F13/10 ,  G06F13/14

    CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F2213/0038

    摘要： A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.

    摘要翻译： 提供了一种用于对包括CPU，MMU，包括源，目的地和大小寄存器的DMA控制器的芯片上的系统的DMA控制器进行编程的程序，以及每个由物理地址标识并可通过应用该物理地址来寻址的实体 物理地址到地址总线。 响应于用户程序的第一专用指令，将虚拟地址转换为对应的物理地址，将对应的物理地址应用于地址总线，具有第一值的信号被传送到DMA控制器，并且信号 具有第二个值被传递给实体。 当传送到DMA控制器的信号具有第一个值时，选择DMA控制器的源寄存器或目标寄存器，并将地址总线上相应的物理地址存储在所选寄存器中。

    Translation look-aside buffer supporting mutually untrusted operating systems
    4.
    发明授权
    Translation look-aside buffer supporting mutually untrusted operating systems 有权
    翻译后备缓冲区支持互不信任的操作系统

    公开(公告)号：US07461232B2

    公开(公告)日：2008-12-02

    申请号：US11440706

    申请日：2006-05-24

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

    摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

    摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。

    Translation look-aside buffer
    5.
    发明申请
    Translation look-aside buffer 有权
    翻译后备缓冲区

    公开(公告)号：US20060271760A1

    公开(公告)日：2006-11-30

    申请号：US11440706

    申请日：2006-05-24

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036 ,  G06F2212/681 ,  Y02D10/13

    摘要： A translation look-aside buffer that stores address translations each of which associate a VPN with a PPN, and which are usable in a first mode of operation of a processor incorporating the buffer for accessing data stored in physical memory. Each entry in the buffer includes a first field for storing the VPN, a second field for storing an intermediate address portion IPN, and a third field for storing the PPN. The first field and the third field are mutually associated via the second field. The buffer is addressable in the first mode of operation of the processor by the content of the first fields. In response to a request for access to eternal memory, it outputs the PPN stored in the third field of a given entry when it is addressed by an input value corresponding to the VPN stored in the first field of said entry.

    摘要翻译： 一种翻译后备缓冲器，其存储每个将VPN与PPN相关联的地址转换，并且可以在包含用于访问存储在物理存储器中的数据的缓冲器的处理器的第一操作模式中使用。 缓冲器中的每个条目包括用于存储VPN的第一字段，用于存储中间地址部分IPN的第二字段和用于存储PPN的第三字段。 第一个字段和第三个字段通过第二个字段相互关联。 缓冲器可以通过第一场的内容在处理器的第一操作模式下寻址。 响应于访问永久存储器的请求，当通过与存储在所述条目的第一字段中的VPN相对应的输入值来寻址存储在给定条目的第三字段中的PPN。

    MEMORY AREA PROTECTION CIRCUIT
    6.
    发明申请
    MEMORY AREA PROTECTION CIRCUIT 有权
    存储区保护电路

    公开(公告)号：US20080155188A1

    公开(公告)日：2008-06-26

    申请号：US11958958

    申请日：2007-12-18

    申请人： Stephan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

    发明人： Stephan Courcambeck ,  Albert Martinez ,  Jean Nicolai ,  William Orlando

    IPC分类号： G06F9/30 ,  G06F12/02

    CPC分类号： G06F12/1483 ,  G06F21/79

    摘要： A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

    摘要翻译： 一种用于控制对由程序执行单元可访问的存储器的至少一个区域的访问的电路，包括第一指令地址输入; 至少一个第二数据地址输入，来自执行单元的地址; 至少一个这些地址相关的功能; 以及用于验证由相关函数设置的条件的满足的位的至少一个输出。

    Procedure for programming a DMA controller in a system on a chip and associated system on a chip
    8.
    发明申请
    Procedure for programming a DMA controller in a system on a chip and associated system on a chip 有权
    在芯片上的系统和芯片上的相关系统上对DMA控制器进行编程的过程

    公开(公告)号：US20060020719A1

    公开(公告)日：2006-01-26

    申请号：US11179033

    申请日：2005-07-11

    申请人： Albert Martinez ,  Jean Nicolai

    发明人： Albert Martinez ,  Jean Nicolai

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F12/1081

    摘要： A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base subaddress. In response to a first instruction of a user program that includes a virtual address, the virtual address is translated into a corresponding physical address, and the physical address is stored in a buffer register that is inaccessible to the user program. In response to a second instruction of the user program, the physical address stored in the buffer register is applied to the data bus and a first word including high-order bits indicating the base subaddress is applied to the address bus. The source or destination register is selected according to the first word applied to the address bus and the physical address applied to the data bus is stored in the selected register.

    摘要翻译： 一种用于对包括CPU，MMU和DMA控制器的芯片上的系统的DMA控制器进行编程的方法，包括与基本子地址相关联的源，目的地和大小寄存器。 响应于包括虚拟地址的用户程序的第一指令，虚拟地址被转换成对应的物理地址，物理地址存储在用户程序不可访问的缓冲寄存器中。 响应于用户程序的第二指令，存储在缓冲寄存器中的物理地址被施加到数据总线，并且包括指示基本子地址的高位的第一个字被施加到地址总线。 源或目标寄存器根据应用于地址总线的第一个字来选择，并且应用于数据总线的物理地址存储在所选择的寄存器中。

    Integrated circuit with mode detection pin for tristate level detection
    9.
    发明授权
    Integrated circuit with mode detection pin for tristate level detection 失效
    具有模式检测PIN的集成电路，用于三次电平检测

    公开(公告)号：US5198707A

    公开(公告)日：1993-03-30

    申请号：US705375

    申请日：1991-05-24

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： G01R31/317

    CPC分类号： G01R31/31701

    摘要： To enable a determined mode of operation, out of several possible modes, to be dictated from the exterior of an integrated circuit, there is provided a specific pin and a detector that is connected to the pin and is capable of detecting a logic level 0 or 1 or a high impedance state at this pin. The detector includes several switches and a resistor. It works in two successive phases and consumes no current at rest. A register memorizes the logic level of the pin during the two phases, and a decoder determines the state of the pin from the two memorized logic levels.

    摘要翻译： 为了使得能够从集成电路的外部指定的几种可能模式中的确定的操作模式，提供了连接到引脚并且能够检测逻辑电平0或1的逻辑电平的特定引脚和检测器 1或该引脚处的高阻抗状态。 检测器包括几个开关和一个电阻。 它连续两个阶段工作，消耗静止电流。 寄存器在两个阶段存储引脚的逻辑电平，解码器从两个存储的逻辑电平确定引脚的状态。

    Method for inserting synchronization markers into a video stream, compatible with a block cipher
    10.
    发明授权
    Method for inserting synchronization markers into a video stream, compatible with a block cipher 有权
    将同步标记插入到与块密码兼容的视频流中的方法

    公开(公告)号：US07787624B2

    公开(公告)日：2010-08-31

    申请号：US11331579

    申请日：2006-01-13

    申请人： Jean Nicolai

    发明人： Jean Nicolai

    IPC分类号： H04N7/167 ,  H04K1/00

    CPC分类号： H04N7/1675 ,  H04N21/23614 ,  H04N21/23897 ,  H04N21/4348 ,  H04N21/8455

    摘要： A method inserts synchronization markers into a standardized stream of compressed and ciphered data, wherein at least one part of the compressed data stream is ciphered bit by bit, by block cipher, and wherein a synchronization marker is only inserted into the compressed data stream after the number of ciphered bits has reached or exceeded the number of bits of the cipher block.

    摘要翻译： 一种方法将同步标记插入压缩和加密数据的标准化流中，其中压缩数据流的至少一部分通过分组密码逐位加密，并且其中同步标记仅在 加密比特数已经达到或超过密码块的比特数。