公开(公告)号：US06658578B1

公开(公告)日：2003-12-02

申请号：US09410977

申请日：1999-10-01

申请人： Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

发明人： Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

IPC分类号： G06F132

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30083 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891 ,  G06K13/0825

摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

摘要翻译： 提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。 架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。 处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。 双乘法累加块提高了处理性能。 存储器接口单元（104）提供对数据和指令存储器的并行访问。 指令缓冲器可用于在执行它之前缓冲单个和复合指令。 解码机构被配置为对来自指令缓冲器的指令进行解码。 使用复合指令可以有效地利用处理器内可用的带宽。 可以从单独的第一和第二编程存储器指令编译软双存储器指令。 可以有条件地执行或重复执行指令。 位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。 处理器包括具有管道保护功能的多级执行管线。 各种功能模块可以单独断电以节省电力。 处理器包括仿真和代码调试功能，支持缓存分析。

公开(公告)号：US06487576B1

公开(公告)日：2002-11-26

申请号：US09411466

申请日：1999-10-01

申请人： Jean-Pierre Giacalone ,  Herve Catan ,  Anne Lombardot

发明人： Jean-Pierre Giacalone ,  Herve Catan ,  Anne Lombardot

IPC分类号： G06F700

CPC分类号： G06F7/508 ,  G06F5/01 ,  G06F7/02 ,  G06F7/49905 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F7/764 ,  G06F9/30094 ,  G06F9/3013

摘要： A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result 479 prior to the arithmetic unit completing an arithmetic operation.

摘要翻译： 用于处理引擎的运算单元42的零预期机制包括互连的单元阵列420,430，以产生中间预期信号的有序序列。 单元阵列包括连接以从运算单元接收中间结果信号的单元，用于转发提供给其的中间预期信号的单元，以及用于产生提供给其的第一中间预期信号和第二中间预期信号的组合的单元。 零预期机制实现零预先机制，其可以在算术单元完成算术运算之前预测零结果479。

公开(公告)号：US06363470B1

公开(公告)日：2002-03-26

申请号：US09411187

申请日：1999-10-01

申请人： Gilbert Laurenti ,  Karim Djafarian ,  Herve Catan

发明人： Gilbert Laurenti ,  Karim Djafarian ,  Herve Catan

IPC分类号： G06F1200

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F5/10 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/3552 ,  G06F9/3879 ,  G06F9/3891

摘要： Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer management logic 802 is configured to be operable to apply a modifier to a virtual buffer index held in the address storage to derive a modified virtual buffer index and to apply a buffer offset held in the offset storage to the modified virtual buffer index to derive a physical address for addressing a circular buffer. By employing virtual addressing to a buffer index for a circular buffer management, it is possible to make efficient use of memory resources. One or more circular buffers can be located contiguously with respect to each other and/or other data in memory, avoiding fragmentation of the memory. The buffer index forms a pointer for the circular buffer. The apparatus enables circular buffers to be implemented without alignment constraints, while maintaining compatibility with prior circular buffer implementations with alignment constraints.

摘要翻译： 支持循环缓冲器CB的数据处理装置10包括用于保持虚拟缓冲器索引的地址存储器ARx和用于保持偏移地址的偏移存储器BOFxx。 循环缓冲器管理逻辑802被配置为可操作以将修饰符应用于保存在地址存储器中的虚拟缓冲器索引，以导出修改的虚拟缓冲器索引并将保持在偏移存储器中的缓冲器偏移应用于修改的虚拟缓冲器索引以导出 用于寻址循环缓冲区的物理地址。 通过对循环缓冲器管理的缓冲器索引采用虚拟寻址，可以有效地利用存储器资源。 可以相对于彼此和/或存储器中的其他数据连续地定位一个或多个循环缓冲器，以避免存储器的碎片化。 缓冲区索引形成循环缓冲区的指针。 该装置使得能够实现循环缓冲器而不具有对准限制，同时保持与具有对准约束的先前循环缓冲器实现的兼容性。

公开(公告)号：US20130128975A1

公开(公告)日：2013-05-23

申请号：US13330417

申请日：2011-12-19

申请人： Ajit Deepak Gupte ,  Hetul Sanghvi ,  Herve Catan

发明人： Ajit Deepak Gupte ,  Hetul Sanghvi ,  Herve Catan

IPC分类号： H04N7/32

CPC分类号： H04N19/513 ,  H04N19/124 ,  H04N19/433 ,  H04N19/44 ,  H04N19/593 ,  H04N19/625

摘要： A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.

摘要翻译： 一种用于在存储器中组织像素信息的系统和方法。 根据本公开的实施例的方法包括将表示场景的像素的数据存储在片上存储器中的参考帧的增长窗口（“GW”）部分中，将表示视觉场景的像素的数据存储在 滑动窗口（“SW”），从而形成混合窗口，搜索存储器以定位与描述场景的当前帧中代表像素的数据相对应的存储数据的一部分，根据 搜索结果，根据运动估计的结果产生当前帧的压缩版本，并存储压缩版本供以后的视觉呈现。 该系统包括处理单元和视频编码器。 处理单元包括片上存储器。 视频编码器包括运动估计引擎和压缩单元。

公开(公告)号：US06681319B1

公开(公告)日：2004-01-20

申请号：US09410653

申请日：1999-10-01

申请人： Karim Djafarian ,  Gilbert Laurenti ,  Herve Catan ,  Vincent Gillet

发明人： Karim Djafarian ,  Gilbert Laurenti ,  Herve Catan ,  Vincent Gillet

IPC分类号： G06F930

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/32 ,  G06F9/321 ,  G06F9/3552 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891

摘要： A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. A compound address field of the predetermined compound instruction can be arranged at the same bit positions as the address field for a hard compound memory instruction, that is a compound instruction which is programmed. In this case the decoding of the addresses can be started before the operation code of the instructions have been decoded. To reduce the number of bits in the compound instruction, addressing can be restricted to indirect addressing and the operation codes for at least the first instruction can be reduced in size. In this way, the compound instruction can be arranged to have the same number of bits in total as the sum of the bits of the separate programmed instructions.

摘要翻译： 处理引擎10包括指令缓冲器502，其可操作用于在执行之前缓冲单个和复合指令。 解码机构被配置为解码来自指令缓冲器的指令。 解码机构被布置成响应于指令的标签字段中的预定标签，该预定标签表示作为由单独的编程存储器指令形成的复合指令的指令。 解码机制可响应于预定标签而操作，以对第一编程指令和第二编程指令的第二数据流控制进行至少第一数据流控制解码。 使用复合指令可以有效利用处理引擎内可用的带宽。 可以从单独的第一和第二编程存储器指令编译软双存储器指令。 预定复合指令的复合地址字段可以被布置在与用于硬化合物存储器指令的地址字段相同的位位置，即，被编程的复合指令。 在这种情况下，可以在指令的操作代码被解码之前开始地址的解码。 为了减少复合指令中的位数，可以将寻址限制为间接寻址，并且可以减小至少第一条指令的操作码的大小。 以这种方式，复合指令可以被布置为具有与分离的编程指令的位的总和相同数量的位。

公开(公告)号：US09204157B2

公开(公告)日：2015-12-01

申请号：US13330417

申请日：2011-12-19

申请人： Ajit Deepak Gupte ,  Hetul Sanghvi ,  Herve Catan

发明人： Ajit Deepak Gupte ,  Hetul Sanghvi ,  Herve Catan

IPC分类号： H04N19/433 ,  H04N19/593

CPC分类号： H04N19/513 ,  H04N19/124 ,  H04N19/433 ,  H04N19/44 ,  H04N19/593 ,  H04N19/625

摘要： A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.

摘要翻译： 一种用于在存储器中组织像素信息的系统和方法。 根据本公开的实施例的方法包括将表示场景的像素的数据存储在片上存储器中的参考帧的增长窗口（“GW”）部分中，将代表视觉场景的像素的数据存储在 滑动窗口（“SW”），从而形成混合窗口，搜索存储器以定位与描述场景的当前帧中代表像素的数据相对应的存储数据的一部分，根据 搜索结果，根据运动估计的结果产生当前帧的压缩版本，并存储压缩版本供以后的视觉呈现。 该系统包括处理单元和视频编码器。 处理单元包括片上存储器。 视频编码器包括运动估计引擎和压缩单元。

公开(公告)号：US06826679B1

公开(公告)日：2004-11-30

申请号：US09716493

申请日：2000-11-20

申请人： Gilbert Laurenti ,  Vincent Gillet ,  Herve Catan

发明人： Gilbert Laurenti ,  Vincent Gillet ,  Herve Catan

IPC分类号： G06F1202

CPC分类号： G06F9/30047 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3853

摘要： A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A coefficient data pointer is provided for accessing coefficient data for use in a multiply-accumulate (MAC) unit. Monitoring circuitry determines when the coefficient data pointer is modified (step 1104). When an instruction is executed (step 1102) that requires a coefficient datum from memory in accordance with the coefficient data pointer, a memory access is inhibited (step 1108) if the coefficient data pointer has not been modified since the last time a memory fetch was made in accordance with the coefficient data pointer and the previously fetched coefficient datum is reused. However, if the coefficient data pointer was modified since the last time a memory fetch was made in accordance with the coefficient data pointer, then the required coefficient datum is fetched from memory (step 1106). A shadow register within the MAC unit execution pipeline temporarily saves coefficient data for possible reuse.

摘要翻译： 提供了一种处理器，它是一个具有可变指令长度的可编程数字信号处理器（DSP），既提供高密码密码又易于编程。 架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。 系数数据指针被提供用于访问在乘法累加（MAC）单元中使用的系数数据。 监视电路确定何时修改系数数据指针（步骤1104）。 当根据系数数据指针执行需要来自存储器的系数数据的指令（步骤1102）时，如果系数数据指针自上次存储器提取时间以来未被修改，则禁止存储器访问（步骤1108） 根据系数数据指针和先前获取的系数数据进行重新使用。 然而，如果从根据系数数据指针进行存储器提取的最后一次修改系数数据指针，则从存储器取出所需的系数数据（步骤1106）。 MAC单元执行管道内的影子寄存器临时保存系数数据，以便重新使用。