公开(公告)号：US08095907B2

公开(公告)日：2012-01-10

申请号：US11874950

申请日：2007-10-19

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

公开(公告)号：US20090106712A1

公开(公告)日：2009-04-23

申请号：US11874950

申请日：2007-10-19

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

公开(公告)号：US20120105240A1

公开(公告)日：2012-05-03

申请号：US13344178

申请日：2012-01-05

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G08B21/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

摘要翻译： 使用片上参数监视器的可靠性评估和系统故障警告的方法。 该方法包括通过识别应力应答的关键参数问题来确定参数变化对可靠性的影响，识别每个参数的参数宏，以及识别布局敏感的评估区域。 该过程还可以包括一组测试点或要压力的产品中的参数宏，在开始应力之前和每次读出压力时测试一组参数宏，并设置技术的寿命参数轮廓。

公开(公告)号：US08504975B2

公开(公告)日：2013-08-06

申请号：US13344178

申请日：2012-01-05

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert McMahon

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/2894

摘要： A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

公开(公告)号：US07656182B2

公开(公告)日：2010-02-02

申请号：US11689150

申请日：2007-03-21

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/2831 ,  G01R31/30

摘要： Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.

摘要翻译： 公开了测试方法实施例，其中在后制造测试中，参数测量取自片上参数测量元件，并用于优化制造在线参数控制学习和/或优化产品筛选过程。 具体来说，这些后期制造参数测量可用于配置芯片，而不会丢弃不合格的产品，而不会丢弃符合要求的产品，并且不需要高成本的功能测试。 它们也可以用于识别来自设计的参数变化的产量敏感性，并且基于产量灵敏度为制造线改进提供反馈。 此外，关于在制造和制造后水平上监测的关键参数的历史数据库可用于预测未来产量，从而预先改进生产线和/或更新供应链预测。

公开(公告)号：US20080231307A1

公开(公告)日：2008-09-25

申请号：US11689150

申请日：2007-03-21

申请人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

发明人： Jeanne P. Bickford ,  John R. Goss ,  Nazmul Habib ,  Robert J. McMahon

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/2831 ,  G01R31/30

摘要： Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.

摘要翻译： 公开了测试方法实施例，其中在后制造测试中，参数测量取自片上参数测量元件，并用于优化制造在线参数控制学习和/或优化产品筛选过程。 具体来说，这些后期制造参数测量可用于配置芯片，而不会丢弃不合格的产品，而不会丢弃符合要求的产品，并且不需要高成本的功能测试。 它们也可以用于识别来自设计的参数变化的产量敏感性，并且基于产量灵敏度为制造线改进提供反馈。 此外，关于在制造和制造后水平上监测的关键参数的历史数据库可用于预测未来产量，从而预先改进生产线和/或更新供应链预测。

公开(公告)号：US20130113514A1

公开(公告)日：2013-05-09

申请号：US13288269

申请日：2011-11-03

申请人： Theodoros E. Anemikos ,  Jeanne P. Bickford ,  Nazmul Habib ,  Susan K. Lichtensteiger

发明人： Theodoros E. Anemikos ,  Jeanne P. Bickford ,  Nazmul Habib ,  Susan K. Lichtensteiger

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： H03K19/0013

摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

公开(公告)号：US08421495B1

公开(公告)日：2013-04-16

申请号：US13288269

申请日：2011-11-03

申请人： Theodoros E. Anemikos ,  Jeanne P. Bickford ,  Nazmul Habib ,  Susan K. Lichtensteiger

发明人： Theodoros E. Anemikos ,  Jeanne P. Bickford ,  Nazmul Habib ,  Susan K. Lichtensteiger

IPC分类号： H03K19/003

CPC分类号： H03K19/0013

摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非易失性存储介质存储电压仓的边界作为速度分级测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

公开(公告)号：US07803644B2

公开(公告)日：2010-09-28

申请号：US11853976

申请日：2007-09-12

申请人： Bruce W. Balch ,  Jeanne P. Bickford ,  Nazmul Habib ,  Phung T. Nguyen

发明人： Bruce W. Balch ,  Jeanne P. Bickford ,  Nazmul Habib ,  Phung T. Nguyen

IPC分类号： H01L21/00

CPC分类号： H01L22/14

摘要： Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

摘要翻译： 公开了在掩模版变化和相关掩模版之间建模的方法。 该方法的一个实施例包括定义跨多个芯片晶片的确定测试; 识别用于进行测试的测量结构; 使用包括所述掩模版上的所述多个芯片的拷贝之间的测量结构的掩模版在所述多芯片晶片上实施所述测量结构，其中所述多个芯片中没有一个覆盖所述掩模版的整体; 使用测量结构在多芯片晶片上进行测试以获得横跨标线的数据; 使用来自表演的数据建立跨越掩模版变化模型; 并且使用横跨掩模版变化模型来预测多个芯片中的至少一个的跨芯片变化。

公开(公告)号：US20090068772A1

公开(公告)日：2009-03-12

申请号：US11853976

申请日：2007-09-12

申请人： Bruce W. Balch ,  Jeanne P. Bickford ,  Nazmul Habib ,  Phung T. Nguyen

发明人： Bruce W. Balch ,  Jeanne P. Bickford ,  Nazmul Habib ,  Phung T. Nguyen

IPC分类号： H01L21/66

CPC分类号： H01L22/14

摘要： Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

摘要翻译： 公开了在掩模版变化和相关掩模版之间建模的方法。 该方法的一个实施例包括定义跨多个芯片晶片的确定测试; 识别用于进行测试的测量结构; 使用包括所述掩模版上的所述多个芯片的拷贝之间的测量结构的掩模版在所述多芯片晶片上实施所述测量结构，其中所述多个芯片中没有一个覆盖所述掩模版的整体; 使用测量结构在多芯片晶片上进行测试以获得横跨标线的数据; 使用来自表演的数据建立跨越掩模版变化模型; 并且使用横跨掩模版变化模型来预测多个芯片中的至少一个的跨芯片变化。