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公开(公告)号：US07803644B2
公开(公告)日：2010-09-28
申请号：US11853976
申请日：2007-09-12
IPC分类号： H01L21/00
CPC分类号： H01L22/14
摘要： Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.
摘要翻译： 公开了在掩模版变化和相关掩模版之间建模的方法。 该方法的一个实施例包括定义跨多个芯片晶片的确定测试; 识别用于进行测试的测量结构; 使用包括所述掩模版上的所述多个芯片的拷贝之间的测量结构的掩模版在所述多芯片晶片上实施所述测量结构，其中所述多个芯片中没有一个覆盖所述掩模版的整体; 使用测量结构在多芯片晶片上进行测试以获得横跨标线的数据; 使用来自表演的数据建立跨越掩模版变化模型; 并且使用横跨掩模版变化模型来预测多个芯片中的至少一个的跨芯片变化。
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公开(公告)号：US20090068772A1
公开(公告)日：2009-03-12
申请号：US11853976
申请日：2007-09-12
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.
摘要翻译： 公开了在掩模版变化和相关掩模版之间建模的方法。 该方法的一个实施例包括定义跨多个芯片晶片的确定测试; 识别用于进行测试的测量结构; 使用包括所述掩模版上的所述多个芯片的拷贝之间的测量结构的掩模版在所述多芯片晶片上实施所述测量结构，其中所述多个芯片中没有一个覆盖所述掩模版的整体; 使用测量结构在多芯片晶片上进行测试以获得横跨标线的数据; 使用来自表演的数据建立跨越掩模版变化模型; 并且使用横跨掩模版变化模型来预测多个芯片中的至少一个的跨芯片变化。
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3.发明授权SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD 有权具有良好触点和P +扩散与SRAM接地或N +扩散穿过VDD的SRAM单元公开(公告)号：US06856031B1
公开(公告)日：2005-02-15
申请号：US10771824
申请日：2004-02-03
申请人： Phung T. Nguyen , Robert C. Wong
发明人： Phung T. Nguyen , Robert C. Wong
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields. The SRAM cell comprises cross coupled pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply VDD, and the N1, N2 devices being coupled through a P+ diffusion region to ground. A first passgate is coupled between a first bitline and the junction of the devices P1 and N1, with its gate coupled to a wordline, and a second passgate is coupled between a second bitline and the junction of devices P2 and N2, with its gate coupled to the wordline.
摘要翻译： 公开了一种低成本的SRAM（静态随机存取存储器）单元，其具有P阱和N阱接触，并且优选地具有与接地的P +扩散交叉。 SRAM单元在M2金属级完成，并具有改进的单元通道泄漏，功能和制造成品率。 SRAM单元包括交叉耦合pnp上拉器件P1，P2和npn下拉器件N1，N2，其中P1，P2器件连接到电源VDD，并且N1，N2器件通过P +扩散耦合 地区到地面 第一通路门耦合在第一位线和器件P1和N1的结点之间，其栅极耦合到字线，并且第二通路门耦合在第二位线和器件P2和N2的结之间，其栅极耦合 到字线
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公开(公告)号：US5258640A
公开(公告)日：1993-11-02
申请号：US939214
申请日：1992-09-02
IPC分类号： H01L29/739 , H01L29/48 , H01L29/56
CPC分类号： H01L29/7391
摘要： An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.
摘要翻译： 集成栅极和半导体势垒层二极管，当栅极截止时用作正常二极管，并且作为肖特基势垒二极管导通。
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公开(公告)号：US20120139056A1
公开(公告)日：2012-06-07
申请号：US13370523
申请日：2012-02-10
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。
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公开(公告)号：US06373221B2
公开(公告)日：2002-04-16
申请号：US09748898
申请日：2000-12-27
IPC分类号： H01M1046
摘要： A charger coupling for charging a battery includes a paddle and a receptacle. The paddle and the receptacle exchange information by radio waves. The paddle includes waveguides for guiding radio waves between an antenna of the paddle and an antenna or the receptacle. The waveguides improve the radio communication between the paddle and the receptacle.
摘要翻译： 用于对电池充电的充电器耦合器包括桨和容器。 桨和容器通过无线电波交换信息。 桨包括用于在桨的天线和天线或插座之间引导无线电波的波导。 波导改善了桨和容器之间的无线电通信。
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7.发明授权Method of forming bipolar transistor integrated with metal gate CMOS devices 失效与金属栅极CMOS器件集成的双极晶体管的形成方法公开(公告)号：US08129234B2
公开(公告)日：2012-03-06
申请号：US12556205
申请日：2009-09-09
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。
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公开(公告)号：US06980009B2
公开(公告)日：2005-12-27
申请号：US10605732
申请日：2003-10-22
CPC分类号： G01R31/2831 , G01R27/2605 , G01R31/2648 , G01R31/2851
摘要： Disclosed is an on-chip test device for testing the thickness of gate oxides in transistors. A ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The difference between the voltages provides a measurement of capacitance of the gate oxide. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. The capacitance of the gate oxide comprises the inverse of the frequency of the ring oscillator output multiplied by the difference between the voltages, less a capacitance constant for the test device. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide. The measurement of capacitance of the gate oxide is used to determine the thickness of the gate oxide.
摘要翻译： 公开了用于测试晶体管中的栅极氧化物的厚度的片上测试装置。 环形振荡器提供环形振荡器输出，反相器接收环形振荡器输出作为输入。 逆变器耦合到栅极氧化物，反相器接收不同的电压作为电源。 电压之间的差异提供了栅极氧化物的电容的测量。 电压之间的差值小于或等于提供给环形振荡器的第二组电压之差的大约三分之一。 栅极氧化物的电容包括环形振荡器输出的频率乘以电压之间的差异的反比，较小的是测试装置的电容常数。 该电容常数用于单独的测试装置，并且不包括栅极氧化物的电容的任何部分。 栅极氧化物的电容的测量用于确定栅极氧化物的厚度。
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公开(公告)号：US06797569B2
公开(公告)日：2004-09-28
申请号：US10249917
申请日：2003-05-19
申请人： David B. Colavito , Nivo Rovedo , Phung T. Nguyen
发明人： David B. Colavito , Nivo Rovedo , Phung T. Nguyen
IPC分类号： H01L21336
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/0649 , H01L29/1037 , H01L29/42376 , H01L29/66628 , H01L29/66651 , H01L29/7835
摘要： A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.
摘要翻译： 公开了一种形成平面化场效应晶体管（FET）的方法。 在本发明的示例性实施例中，所述方法包括在衬底上限定有源半导体区域，所述有源半导体区域还包括一对台面区域。 源区域被限定在一对台面区域之一的顶表面内，并且漏区域限定在该对台面区域中另一个的顶表面内。 然后，在一对台面区域之间沉积栅极材料，并且栅极材料被平坦化以形成栅极。 由此，栅极的顶表面与源极和漏极区域基本上是平面的。
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公开(公告)号：US08569840B2
公开(公告)日：2013-10-29
申请号：US13370523
申请日：2012-02-10
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。
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