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1.发明授权Integrated circuit product yield optimization using the results of performance path testing 有权集成电路产品产量优化使用性能路径测试的结果公开(公告)号：US09058034B2
公开(公告)日：2015-06-16
申请号：US13570285
申请日：2012-08-09
IPC分类号： G06F17/50 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。
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2.发明申请DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING 有权使用性能排序振荡器和性能路径测试处理集成电路公开(公告)号：US20130125076A1
公开(公告)日：2013-05-16
申请号：US13294220
申请日：2011-11-11
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译： 一种配置集成电路芯片的方法和系统。 该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。
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3.发明申请INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权使用性能路径测试结果的集成电路产品线优化公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。
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4.发明授权System yield optimization using the results of integrated circuit chip performance path testing 有权系统产量优化采用集成电路芯片性能路径测试的结果公开(公告)号：US08539429B1
公开(公告)日：2013-09-17
申请号：US13572954
申请日：2012-08-13
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725
摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
摘要翻译： 公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。 在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关 其中包含先前经过性能路径测试的那些IC芯片。 基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统 满足目标系统的性能价值）。 可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。
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5.发明授权Test path selection and test program generation for performance testing integrated circuit chips 有权测试路径选择和测试程序生成用于性能测试集成电路芯片公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。
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6.发明授权Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权使用性能分类环形振荡器和性能路径测试对集成电路进行处理公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译： 一种配置集成电路芯片的方法和系统。 该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。
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7.发明申请TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权性能测试集成电路卡的测试路径选择和测试程序生成公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径
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公开(公告)号：US09157956B2
公开(公告)日：2015-10-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G01R31/317 , G01R31/30
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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9.发明授权公开(公告)号：US08726201B2
公开(公告)日：2014-05-13
申请号：US12780138
申请日：2010-05-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/10
摘要： A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.
摘要翻译： 一种用于预测半导体产品中多个电迁移关键元件的方法和系统。 该方法包括使用运行在计算机设备上的设计工具并且基于增加的可靠性温度和增加的预期电流中的至少一个来确定电路设计库中的多个库元件的关键要素因子。 该方法还包括：（i）产品中包含的多个库元素中的相应数量的数量，以及（ii）关键要素因素来确定产品中的关键元素的数量。
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公开(公告)号：US20140074422A1
公开(公告)日：2014-03-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F19/00 , G01R31/317
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。
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