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    Test path selection and test program generation for performance testing integrated circuit chips
    2.
    发明授权
    Test path selection and test program generation for performance testing integrated circuit chips 有权
    测试路径选择和测试程序生成用于性能测试集成电路芯片

    公开(公告)号：US08543966B2

    公开(公告)日：2013-09-24

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F11/22 ,  G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS
    4.
    发明申请
    TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
    性能测试集成电路卡的测试路径选择和测试程序生成

    公开(公告)号：US20130125073A1

    公开(公告)日：2013-05-16

    申请号：US13294210

    申请日：2011-11-11

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31726 ,  G01R31/318541

    摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths

    摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

    Integrated circuit product yield optimization using the results of performance path testing
    5.
    发明授权
    Integrated circuit product yield optimization using the results of performance path testing 有权
    集成电路产品产量优化使用性能路径测试的结果

    公开(公告)号：US09058034B2

    公开(公告)日：2015-06-16

    申请号：US13570285

    申请日：2012-08-09

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

    IPC分类号： G06F17/50 ,  G05B19/418

    CPC分类号： G05B19/41875 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/32208 ,  G05B2219/37224 ,  Y02P80/30 ,  Y02P90/22

    摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

    摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。

    INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING
    6.
    发明申请
    INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
    使用性能路径测试结果的集成电路产品线优化

    公开(公告)号：US20140046466A1

    公开(公告)日：2014-02-13

    申请号：US13570285

    申请日：2012-08-09

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

    IPC分类号： G05B19/18

    CPC分类号： G05B19/41875 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/32208 ,  G05B2219/37224 ,  Y02P80/30 ,  Y02P90/22

    摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

    摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。

    System yield optimization using the results of integrated circuit chip performance path testing
    9.
    发明授权
    System yield optimization using the results of integrated circuit chip performance path testing 有权
    系统产量优化采用集成电路芯片性能路径测试的结果

    公开(公告)号：US08539429B1

    公开(公告)日：2013-09-17

    申请号：US13572954

    申请日：2012-08-13

    申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar

    发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31718 ,  G01R31/31725

    摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.

    摘要翻译： 公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。 在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关 其中包含先前经过性能路径测试的那些IC芯片。 基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统 满足目标系统的性能价值）。 可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。

    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage
    10.
    发明授权
    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
    用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法

    公开(公告)号：US07856607B2

    公开(公告)日：2010-12-21

    申请号：US11934146

    申请日：2007-11-02

    申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F11/24 ,  G01R31/31835

    摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

    摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。