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公开(公告)号：US20060113625A1
公开(公告)日：2006-06-01
申请号：US10999704
申请日：2004-11-30
申请人： Jeff Bude , Isik Kizilyalli , Kent Smith
发明人： Jeff Bude , Isik Kizilyalli , Kent Smith
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/402
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.0e12 atoms/cm2. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device.
摘要翻译： 形成MOS器件，其包括第一导电类型的半导体层，以及形成在半导体层中的靠近半导体层的上表面的第二导电类型的源区和漏区。 源区和漏区彼此间隔开。 第二导电类型的漂移区形成在靠近半导体层的上表面的半导体层中并且至少部分地在源极和漏极区之间，漂移区具有大于约2.0e12原子/ cm 2的杂质掺杂浓度， SUP> 2 。 绝缘层形成在半导体层的上表面的至少一部分上。 所述器件还包括至少部分地在所述源极和漏极区域之间形成在所述绝缘层上的栅极，以及形成在所述半导体层中的所述第一导电类型的掩埋层彼此靠近并且位于所述漂移区域的至少一部分 。 掩埋层和漂移区之间的基本上垂直的距离和/或掩埋层的一个或多个物理尺寸被配置为优化器件相对于导通电阻和最大值中的至少一个的功率密度 漏极电流。
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公开(公告)号：US20070096146A1
公开(公告)日：2007-05-03
申请号：US11641507
申请日：2006-12-19
IPC分类号： H01L29/43 , H01L29/74 , H01L31/111
CPC分类号： H01L29/4983 , H01L29/812
摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.
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公开(公告)号：US20060071250A1
公开(公告)日：2006-04-06
申请号：US10948897
申请日：2004-09-24
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L29/812
摘要： A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.
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