公开(公告)号：US5742847A

公开(公告)日：1998-04-21

申请号：US331727

申请日：1994-10-31

申请人： Shaun Knoll ,  Jeff Charles Morriss ,  Ajay V. Bhatt ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Sudarshan Bala Cadambi

发明人： Shaun Knoll ,  Jeff Charles Morriss ,  Ajay V. Bhatt ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Sudarshan Bala Cadambi

IPC分类号： G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F13/14 ,  G06F13/20

CPC分类号： H04L12/40058 ,  G06F13/10 ,  G06F13/22 ,  G06F13/4022 ,  H04L12/40065

摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

摘要翻译： 电路和互补逻辑提供给总线控制器，多个1：n总线信号分配器，以及用于总线控制器的分级串行总线组件的多个总线接口，用于动态生成并维护基于帧的轮询时间表，以轮询 总线代理连接到串行总线组件和串行总线元件本身的功能。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑支持总线控制器收集各种关键操作特性。 提供给总线控制器的电路和逻辑依次产生基于帧的轮询调度，这些收集的关键操作特性，保证等时外设的同步功能的延迟和带宽。 在某些实施例中，响应于串行总线元件的实时连接/分离，提供给总线控制器的电路和逻辑进一步适应实时地基于其基于帧的轮询调度。

公开(公告)号：US5694555A

公开(公告)日：1997-12-02

申请号：US619863

申请日：1996-03-19

申请人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

发明人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

CPC分类号： H04L12/40058 ,  G06F13/385 ,  G06F13/4291 ,  H04L12/40071 ,  H04L12/40117 ,  H04L12/40123

摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

摘要翻译： 电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。 数据通信事务使用元素数据包进行，并根据事务协议进行。 在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。 连接管理事务以与数据通信事务相同的方式进行。

公开(公告)号：US5909556A

公开(公告)日：1999-06-01

申请号：US980507

申请日：1997-12-01

申请人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

发明人： Jeff Charles Morriss ,  Shaun Knoll ,  Puthiya Kottal Nizar ,  Richard M. Haslam ,  Ajay V. Bhatt ,  Sudarshan Bala Cadambi

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

CPC分类号： H04L12/40058 ,  G06F13/385 ,  G06F13/4291 ,  H04L12/40071 ,  H04L12/40117 ,  H04L12/40123

摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

摘要翻译： 电路和互补逻辑被提供给总线控制器，多个1：n总线信号分配器，以及用于在互连到分层总线组件的总线代理之间进行数据通信事务的分层总线组件的多个总线接口。 分级串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 串行总线元件的这些电路和互补逻辑实现了许多元件分组和多个事务处理协议，采用事务流控制的主/从模型。 数据通信事务使用元素数据包进行，并根据事务协议进行。 在一些实施例中，串行总线元件的这些电路和互补逻辑也用于在串行总线元件之间进行连接管理事务。 连接管理事务以与数据通信事务相同的方式进行。

公开(公告)号：US5615404A

公开(公告)日：1997-03-25

申请号：US332255

申请日：1994-10-31

申请人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Puthiya K. Nizar ,  Richard M. Haslam ,  Andrew M. Volk ,  Sudarshan B. Cadambi

发明人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Puthiya K. Nizar ,  Richard M. Haslam ,  Andrew M. Volk ,  Sudarshan B. Cadambi

IPC分类号： G06F13/38 ,  G06F13/00 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64 ,  G06F13/12

CPC分类号： H04L12/40058 ,  G06F13/423 ,  H04L12/40078

摘要： A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

摘要翻译： 总线控制器，多个1：n总线信号分配器和多个总线接口被提供用于形成用于将多个等时和异步外设串行连接到计算机系统的系统单元的分层串行总线组件。 总线控制器，总线信号分配器和总线接口具有用于实现流量控制的主/从模型的电路和互补逻辑，用于将总线代理相互连接以进行数据通信事务。 在某些实施例中，这些电路和互补逻辑还进行采用流量控制的主/从模型的连接管理事务，实现用于轮询从设备的基于帧的轮询调度，使用至少两个地址空间来进行各种交易 支持基于通信分组的事务，和/或电表示数据和/或控制状态。

公开(公告)号：US5623610A

公开(公告)日：1997-04-22

申请号：US332375

申请日：1994-10-31

申请人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Sudarshan B. Cadambi

发明人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Sudarshan B. Cadambi

IPC分类号： G06F12/06 ,  G06F13/38 ,  H04L12/40 ,  H04L12/64 ,  G06F12/00 ,  G06F12/02

CPC分类号： H04L12/40058 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/385 ,  H04L12/40078

摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

摘要翻译： 电路和互补逻辑提供给总线控制器，多个1：n总线信号分配器，以及用于总线控制器的分级串行总线组件的多个总线接口，以动态地检测和管理串行总线元件的互连拓扑 。 串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 这些电路和互补逻辑支持串行总线元件的分层视图，逻辑上将层次划分为多层。 串行总线元件的这种逻辑视图被总线控制器用于检测互连的串行总线元件的存在以及总线代理的功能，即系统单元和互连的外设，以及将地址分配给串行总线 元件和功能，在上电，复位和操作期间，当串行总线元件被热连接到串行总线组件或从串行总线组件分离时。