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7 条记录 (耗时 0.022 秒)

    System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
    1.
    发明授权
    System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset 失效
    用于通过启用上游端口并在上电/复位时选择性地启用禁用端口来分配分层串行总线中的地理位置的系统

    公开(公告)号：US5623610A

    公开(公告)日：1997-04-22

    申请号：US332375

    申请日：1994-10-31

    申请人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Sudarshan B. Cadambi

    发明人： Shaun Knoll ,  Jeff C. Morriss ,  Shelagh Callahan ,  Ajay V. Bhatt ,  Sudarshan B. Cadambi

    IPC分类号： G06F12/06 ,  G06F13/38 ,  H04L12/40 ,  H04L12/64 ,  G06F12/00 ,  G06F12/02

    CPC分类号： H04L12/40058 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/385 ,  H04L12/40078

    摘要： Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

    摘要翻译： 电路和互补逻辑提供给总线控制器，多个1：n总线信号分配器，以及用于总线控制器的分级串行总线组件的多个总线接口，以动态地检测和管理串行总线元件的互连拓扑 。 串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 这些电路和互补逻辑支持串行总线元件的分层视图，逻辑上将层次划分为多层。 串行总线元件的这种逻辑视图被总线控制器用于检测互连的串行总线元件的存在以及总线代理的功能，即系统单元和互连的外设，以及将地址分配给串行总线 元件和功能，在上电，复位和操作期间，当串行总线元件被热连接到串行总线组件或从串行总线组件分离时。

    Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
    2.
    发明授权
    Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems 失效
    用于在计算机存储器子系统中有效读取指令代码数据的方法和装置

    公开(公告)号：US5367657A

    公开(公告)日：1994-11-22

    申请号：US955042

    申请日：1992-10-01

    申请人： Manoj Khare ,  Sudarshan B. Cadambi

    发明人： Manoj Khare ,  Sudarshan B. Cadambi

    IPC分类号： G06F9/38 ,  G06F12/02 ,  G06F9/26 ,  G06F9/34 ,  G06F13/00

    CPC分类号： G06F9/3814 ,  G06F12/0215 ,  G06F9/3802

    摘要： A memory subsystem and method are disclosed in which instruction code read-prefetching is implemented in the memory subsystem itself. A single-line read-prefetch buffer is implemented in the memory subsystem. A memory controller includes an address buffer for read-prefetches, and a memory datapath includes a data buffer for read-prefetches. Smart read-prefetching is used in which only code(instruction) reads are prefetched, taking advantage of the sequentiality of code (instruction) type data as well as the page mode feature of dynamic random access memories.

    摘要翻译： 公开了一种存储器子系统和方法，其中在存储器子系统本身中实现了指令代码读取预取。 在内存子系统中实现单行读取预取缓冲区。 存储器控制器包括用于读取预取的地址缓冲器，并且存储器数据路径包括用于读取预取的数据缓冲器。 使用智能读取预取，其中仅使用代码（指令）读取，利用代码（指令）类型数据的顺序性以及动态随机存取存储器的页面模式特征。

    Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
    3.
    发明授权
    Multiprocessor computer system with data bus and ordered and out-of-order split data transactions 失效
    具有数据总线和有序和无序拆分数据事务的多处理器计算机系统

    公开(公告)号：US5191649A

    公开(公告)日：1993-03-02

    申请号：US631892

    申请日：1990-12-21

    申请人： Sudarshan B. Cadambi ,  Charles B. Guy ,  David R. Gray ,  Mark A. Gonzales

    发明人： Sudarshan B. Cadambi ,  Charles B. Guy ,  David R. Gray ,  Mark A. Gonzales

    IPC分类号： G06F15/17

    CPC分类号： G06F15/17

    摘要： A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first data from a second processor. The second processor then determines with which one of (1) the first data and (2) a read response command and the first data it desires to respond to the read command. If the second processor determines to respond with the first data, then it acknowledges receipt of the read command and performs an ordered response in which the command and address buses are released and only the first data is later sent to the first processor via the data bus when available. If the second processor determines to respond with the read response command and the first data, then it acknowledges receipt of the read command and performs an out-of-order response in which the access of the command and address buses is first released and gained again by arbitration when the first data is determined to be available in the second processor. The second processor then gains the access of the data bus when the data bus is free of any data transaction. The read response command and its address and the first data are then issued to the first processor.

    摘要翻译： 描述了在具有耦合到地址总线，命令总线和数据总线的多个处理器的计算机系统中响应于读取命令传送数据的方法。 第一处理器产生并发送读取命令以从第二处理器读取第一数据。 然后，第二处理器确定（1）第一数据中的哪一个和（2）读响应命令及其希望对读命令作出响应的第一数据。 如果第二处理器确定用第一数据进行响应，则其确认读取命令的接收并且执行其中命令和地址总线被释放的有序响应，并且仅第一数据稍后经由数据总线发送到第一处理器 有空的时候。 如果第二处理器确定使用读取响应命令和第一个数据进行响应，则它确认接收到读取命令并且执行无效响应，其中命令和地址总线的访问首先被释放并再次获得 当第一数据被确定为在第二处理器中可用时通过仲裁。 然后当数据总线没有任何数据事务时，第二处理器获得数据总线的访问。 然后，将读取响应命令及其地址和第一数据发布到第一处理器。

    Distributed arbitration method and apparatus for a computer bus using arbitration groups
    7.
    发明授权
    Distributed arbitration method and apparatus for a computer bus using arbitration groups 失效
    使用仲裁组的计算机总线的分布式仲裁方法和装置

    公开(公告)号：US5261109A

    公开(公告)日：1993-11-09

    申请号：US6138

    申请日：1993-01-19

    申请人： Sudarshan B. Cadambi ,  Charles B. Guy ,  David R. Gray ,  Mark A. Gonzales

    发明人： Sudarshan B. Cadambi ,  Charles B. Guy ,  David R. Gray ,  Mark A. Gonzales

    IPC分类号： G06F13/368 ,  G06F13/374 ,  G06F13/36

    CPC分类号： G06F13/374 ,  G06F13/368

    摘要： A distributed method for arbitrating access to a common bus in a multiple processor environment is described. This method provides for fairness where multiple processors are vying for access to a global memory. An apparatus for arbitrating access to a common bus in a multiple processor environment is also described. This apparatus provides for priority determination of each processor upon system reset and provides for fairness where multiple processors are vying for access to a global memory.

    摘要翻译： 描述了用于在多处理器环境中仲裁访问公共总线的分布式方法。 该方法提供了多个处理器争取访问全局内存的公平性。 还描述了用于在多处理器环境中仲裁访问公共总线的装置。 该装置在系统复位时提供每个处理器的优先级确定，并且在多个处理器竞争访问全局存储器时提供公平性。