公开(公告)号：US20110292932A1

公开(公告)日：2011-12-01

申请号：US12788453

申请日：2010-05-27

申请人： Jeffery Thomas Nichols ,  Ian Dublin ,  Peter Bengough ,  Andre Sabourin

发明人： Jeffery Thomas Nichols ,  Ian Dublin ,  Peter Bengough ,  Andre Sabourin

IPC分类号： H04L12/50

CPC分类号： H04L49/103 ,  H04L49/00 ,  H04L49/45 ,  H04Q2213/13393

摘要： The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost). The present invention may include link encoding of switch frames by mapping 8B10B control characters into an 64B65B format (similar to Generic Framing Protocol-Transparent (GFP-T)), wrapping 32 65B encoded words with an 11-bit error correcting code, and scrambling the frame with a frame synchronous scrambler.

摘要翻译： 本公开提供了一种结构化的流水线大时空交换机和解决互连复杂性的操作方法。 时空交换机导致互连复杂度随着空间维度的增加而不增长，并导致长的高扇出网络的减少，更快的布局和改进的时钟速度。 关于时空交换矩阵实现，本发明提高了交换结构的最大时钟频率，并且通过消除长的高扇出网来提高集成电路布局时间。 某些高速大型交换机结构在没有实现的情况下可能无法实现，并且大大降低了实施时间（和成本）。 本发明可以通过将8B10B控制字符映射成64B65B格式（类似于通用帧协议 - 透明（GFP-T）），包括具有11位纠错码的32 65B编码字和加扰，包括交换帧的链路编码 该帧具有帧同步扰频器。

公开(公告)号：US09825883B2

公开(公告)日：2017-11-21

申请号：US12788453

申请日：2010-05-27

申请人： Jeffery Thomas Nichols ,  Ian Dublin ,  Peter Bengough ,  Andre Sabourin

发明人： Jeffery Thomas Nichols ,  Ian Dublin ,  Peter Bengough ,  Andre Sabourin

IPC分类号： H04Q11/00 ,  H04L12/933 ,  H04L12/931

CPC分类号： H04L49/103 ,  H04L49/00 ,  H04L49/45 ,  H04Q2213/13393

摘要： The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost). The present invention may include link encoding of switch frames by mapping 8B10B control characters into an 64B65B format (similar to Generic Framing Protocol-Transparent (GFP-T)), wrapping 32 65B encoded words with an 11-bit error correcting code, and scrambling the frame with a frame synchronous scrambler.

公开(公告)号：US08830993B1

公开(公告)日：2014-09-09

申请号：US13326111

申请日：2011-12-14

申请人： Ian Dublin ,  Jeffery Thomas Nichols ,  Peter Bengough

发明人： Ian Dublin ,  Jeffery Thomas Nichols ,  Peter Bengough

IPC分类号： H04L12/50

CPC分类号： H04L49/103 ,  H04L49/00 ,  H04L49/45

摘要： A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.

摘要翻译： 环形架构中的时空交换机包括输入电路，包括每个接收M个时隙的N个链路的输入电路，多个切换电路的二维矩阵，二维矩阵被配置为从输入电路接收每个M个时隙 以及以流水线方式从N个链路输出的N个链路的输出电路，以及包括N个链路的输出电路，被配置为从二维矩阵中的任何一个N个链路接收任何M个时隙。 输入电路，二维矩阵和输出电路以它们之间的环形结构排列。 在电路中执行的链路编码协议方法包括接收多个时隙，将多个时隙分组成时隙组，在相邻时隙组之间执行循环冗余校验，对时隙组编码64 / 65B，以及前向 从64 / 65B编码对多个65B码字进行纠错编码。

公开(公告)号：US06289044B1

公开(公告)日：2001-09-11

申请号：US09076635

申请日：1998-05-12

申请人： Edgar Velez ,  Ian Dublin ,  Peter Noel

发明人： Edgar Velez ,  Ian Dublin ,  Peter Noel

IPC分类号： H04B138

CPC分类号： H03G3/3052

摘要： An automatic gain control method and apparatus for modem receivers. The automatic gain control circuit includes a programmable loop gain for scaling a digital signal Y to a first prescribed level during a first mode of operation and to a second prescribed level during a second mode of operation; and filters and converters for converting the scaled signal Y into an analog gain control signal for input to the analog AGC. The gain control circuit and method of operation provides control over the parameters of the programmable loop gain such that during start-up initialization the signal Y is scaled to the first prescribed value and during steady state operation the signal Y is scaled to the second prescribed value. This is accomplished by changing the gain parameter of the programmable loop gain.

摘要翻译： 一种用于调制解调器接收机的自动增益控制方法和装置。 所述自动增益控制电路包括可编程环路增益，用于在第一操作模式期间将数字信号Y缩放到第一规定级别，并在第二操作模式期间将其调整到第二规定级别; 以及用于将缩放的信号Y转换成用于输入到模拟AGC的模拟增益控制信号的滤波器和转换器。 增益控制电路和操作方法提供对可编程环路增益的参数的控制，使得在启动初始化期间，信号Y被缩放到第一规定值，并且在稳态操作期间，信号Y被缩放到第二规定值 。 这是通过改变可编程环路增益的增益参数来实现的。

公开(公告)号：US06246722B1

公开(公告)日：2001-06-12

申请号：US09069520

申请日：1998-04-29

申请人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

发明人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

IPC分类号： H04L512

CPC分类号： H04L25/03057 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/037

摘要： A method of detecting misconvergence in an equalizer having a quadrature amplitude modulation (QAM) slicer having an index n. The method includes the steps of initializing a plurality of signal counters then processing random symbols (for example between 500 and 20000 symbols) through the equalizer where the symbols are quantized into an appropriate constellation point in an n-QAM constellation map, where each signal counter corresponds to a respective one of the constellation points in the constellation map. The signal counters are incremented when one of the symbols is quantized to the corresponding constellation point. After the signals have been processed into the constellation map the number of non-zero counters are detected. If the number of non-zero counters is less than a prescribed number (for example between approximately 0.5n and approximately 0.9n), then the equalizer has not converged and if the number of non-zero counters is equal to or greater than the prescribed number than the equalizer has converged.

摘要翻译： 一种在具有索引n的正交幅度调制（QAM）限幅器的均衡器中检测失会聚的方法。 该方法包括以下步骤：初始化多个信号计数器，然后通过均衡器处理随机符号（例如，500到20000个符号之间），其中符号被量化成n-QAM星座图中的适当星座点，其中每个信号计数器 对应于星座图中的星座点中的相应一个。 当其中一个符号被量化到相应的星座点时，信号计数器递增。 在将信号处理成星座图之后，检测非零计数器的数量。 如果非零计数器的数量小于规定数量（例如在大约0.5n和大约0.9n之间），则均衡器没有收敛，并且如果非零计数器的数量等于或大于规定的 数字比均衡器收敛。

公开(公告)号：US06278746B1

公开(公告)日：2001-08-21

申请号：US09076240

申请日：1998-05-12

申请人： Edgar Velez ,  Ian Dublin

发明人： Edgar Velez ,  Ian Dublin

IPC分类号： H04L2722

CPC分类号： H03L7/091 ,  H03D3/006 ,  H03J7/04 ,  H03L7/107 ,  H04L7/0004 ,  H04L7/0335 ,  H04L27/38

摘要： A method and apparatus for timing recovery in modem receivers. The timing recovery circuit includes a voltage controlled oscillator for controlling the voltage controlled sampling frequency of an analog-to-digital converter. The oscillator generates a timing clock that is dependent on an average phase error signal calculated from Nyquist signals of the input signal. A phase detector circuit is used for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals. A digital loop filter receives the instantaneous phase error signal over time to generate the average phase error signal. The average phase error signal is conditioned further (after conversion to analog) by an analog loop filter such that the average phase error signal adjusts the timing clock generated by the oscillator. The low pass filter provides control of the acquisition and steady state operations by changing the gain and pole parameters of the filter. This control enables fast timing acquisition and low noise with reduced phase jitter during steady state operation.

摘要翻译： 一种调制解调器接收机定时恢复的方法和装置。 定时恢复电路包括用于控制模数转换器的压控采样频率的压控振荡器。 振荡器产生取决于由输入信号的奈奎斯特信号计算的平均相位误差信号的定时时钟。 相位检测器电路用于产生同相和正交相位信号的瞬时相位误差信号。 数字环路滤波器随时间接收瞬时相位误差信号以产生平均相位误差信号。 通过模拟环路滤波器进一步调整平均相位误差信号（在转换为模拟之后），使得平均相位误差信号调节由振荡器产生的定时时钟。 低通滤波器通过改变滤波器的增益和极点参数来提供对采集和稳态操作的控制。 该控制可实现快速定时采集和低噪声，同时在稳态运行期间可减少相位抖动。

公开(公告)号：US6163572A

公开(公告)日：2000-12-19

申请号：US69436

申请日：1998-04-29

申请人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

发明人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

IPC分类号： H03H21/00 ,  H04L25/03 ,  H03H7/30

CPC分类号： H04L25/03057 ,  H03H21/0067 ,  H04L2025/03401 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A method of reducing leakage noise introduced to an equalizer in a modem during steady state operation. The equalizer includes forward and feedback filters represented by tap coefficients. The tap coefficients of the filters are updated using least mean squares adaptation equations at a symbol rate during steady state operation. The method of the invention includes the steps of: (a) reducing the absolute value of the updated tap coefficients of the filters at a prescribed rate that is less than the symbol rate. Long term convergence stability is improved and leakage noise is reduced by leaking the filter coefficients less frequently than the symbol rate.

摘要翻译： 一种在稳态运行期间减少调制解调器中的均衡器引入的泄漏噪声的方法。 均衡器包括由抽头系数表示的正向和反馈滤波器。 滤波器的抽头系数在稳态操作期间以符号率的最小均方适应方程更新。 本发明的方法包括以下步骤：（a）以小于符号率的规定速率降低滤波器的更新抽头系数的绝对值。 通过使滤波器系数比符号速率更低频率地泄漏，可以提高长期的会聚稳定性，降低泄漏噪声。

公开(公告)号：US07797464B2

公开(公告)日：2010-09-14

申请号：US11517465

申请日：2006-09-08

申请人： Ian Mes ,  Ian Dublin ,  Christian Bourget

发明人： Ian Mes ,  Ian Dublin ,  Christian Bourget

IPC分类号： G06F3/00 ,  H04L12/56

CPC分类号： G06F13/385 ,  H04M11/062

摘要： A system and method for optimizing the transmission of signals over a group of wires. In a preferred form of the present invention, a multi-wire bus connects a common card to a plurality of line cards. A framing protocol controls transmissions between the common card and the plurality of line cards. The framing protocol includes a frame having a prefix that identifies in which direction a given transmission will occur. The prefix also identifies over which wire or wires a given line card will receive data. Each of the line cards are configured to interpret the prefix so that at any given time data can be transmitted from the common card to one or more of the line cards by either transmission over a single wire or a plurality of wires.

摘要翻译： 一种用于优化一组电线上的信号传输的系统和方法。 在本发明的优选形式中，多线总线将公共卡连接到多个线卡。 成帧协议控制公共卡和多个线卡之间的传输。 成帧协议包括具有前缀的帧，其标识在哪个方向上发生给定的传输。 该前缀还标识给定线卡将接收数据的电线或电线。 每个线路卡被配置为解释前缀，使得在任何给定时间，可以通过单线或多条线路的传输将数据从普通卡发送到一个或多个线路卡。

公开(公告)号：US06266377B1

公开(公告)日：2001-07-24

申请号：US09076634

申请日：1998-05-12

申请人： Edgar Velez ,  Ian Dublin

发明人： Edgar Velez ,  Ian Dublin

IPC分类号： H04L2302

CPC分类号： H04L7/0054 ,  H03L7/095 ,  H04L7/0004 ,  H04L7/0335

摘要： A method of timing recovery convergence monitoring in modems using an average phase error signal. The method involves continuously tracking the peak of the average phase error. The average phase error is compared to a dynamic threshold (i.e. a threshold that can change over time based on changes to the detected peak at a given time). Convergence is declared when the average phase error remains less than the threshold over a given length of time (i.e. after processing a prescribed number of consecutive samples).

摘要翻译： 使用平均相位误差信号的调制解调器中定时恢复收敛监测的方法。 该方法包括连续跟踪平均相位误差的峰值。 将平均相位误差与动态阈值（即，可以基于在给定时间处检测到的峰值的改变而随时间改变的阈值）进行比较。 当平均相位误差在给定的时间长度（即在处理规定数量的连续采样之后）保持小于阈值时，就会声明收敛。

公开(公告)号：US06188722B1

公开(公告)日：2001-02-13

申请号：US09069521

申请日：1998-04-29

申请人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

发明人： Edgar Velez ,  Ian Dublin ,  Richard Buz ,  Sisay Yirga

IPC分类号： H03K5159

CPC分类号： H04L25/0307 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/037 ,  H04L2025/03732

摘要： A blind convergence process for an adaptive decision feedback equalizer having an quadrature amplitude modulation (QAM) slicer, a forward filter defined by a plurality of forward tap coefficients and a feedback filter defined by a plurality of feedback tap coefficients. The blind convergence process includes the step of initializing the forward tap coefficients of the forward filter and the feedback tap coefficients of the feedback filters with predetermined values. The QAM slicer operates in two modes: a clustering mode and a decision directed mode. The clustering mode includes the step of updating only the forward tap coefficients of the forward filter for a prescribed start-up QAM index (such a 4 QAM). The decision directed mode is predefined for set of QAM indexes having values n1, n2, . . . nm, and includes: updating the forward tap coefficients of the forward filter for a QAM index ni selected from the predefined set of QAM indexes, and updating the feedback tap coefficients of the feedback filter for the QAM index ni selected from the predefined set of QAM indexes. The decision directed processing steps are repeating the next QAM index ni+1 of the predefined set of QAM indexes until the equalizer has converged to its highest available QAM index or until the equalizer has converged to the highest operable QAM index (constellation). The QAM index set can be {4,16,64,256}.

摘要翻译： 具有正交幅度调制（QAM）限幅器的自适应判决反馈均衡器的盲收敛过程，由多个正向抽头系数定义的正向滤波器和由多个反馈抽头系数定义的反馈滤波器。 盲收敛处理包括以预定值初始化正向滤波器的正向抽头系数和反馈滤波器的反馈抽头系数的步骤。 QAM切片器以两种模式运行：聚类模式和决策定向模式。 聚类模式包括只针对规定的起始QAM索引（例如4QAM）更新正向滤波器的前向抽头系数的步骤。 对于具有值n1，n2，...的QAM索引的集合，预定义了决策定向模式。 。 。 nm，并且包括：更新从预定义的QAM索引组中选择的QAM索引ni的前向滤波器的前向抽头系数，以及更新从预定义的QAM集合中选择的QAM索引ni的反馈滤波器的反馈抽头系数 索引。 决策指导处理步骤重复预定义的QAM索引集合的下一个QAM索引ni + 1，直到均衡器已经收敛到其最高可用QAM索引或直到均衡器已经收敛到最高可操作的QAM索引（星座）为止。 QAM指数集可以是{4,16,64,256}。