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公开(公告)号：US6045678A
公开(公告)日：2000-04-04
申请号：US847088
申请日：1997-05-01
CPC分类号： C25D7/12
摘要： A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.
摘要翻译： 一种制造纳米丝场发射器件的方法。 该方法能够形成高纵横比，用于场致发射显示器的电镀纳米丝结构器件，其中通孔形成在电介质层中，并且与电介质层顶部的栅极金属结构中的通孔自对准。 电介质层中通孔的理想直径约为50-200nm，纵横比为5-10。 在一个实施例中，在电介质层中形成通孔之后，栅极金属被钝化，之后必要时在通孔的底部沉积电镀增强层。 然后将纳米丝电镀在通孔中，随后除去栅极钝化层，回蚀电介质，并使纳米丝的锐化。 硬掩模层可以沉积在栅极金属的顶部上，并在纳米丝的电镀之后去除。
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公开(公告)号：US6033583A
公开(公告)日：2000-03-07
申请号：US851258
申请日：1997-05-05
CPC分类号： C03C17/3417 , C03C15/00 , C03C17/3482 , C03C2218/33
摘要： A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant. The 20-1000 nm diameter holes resulting from the vapor etching process can be useful as molds for electroplating nanometer-sized filaments, etching gate cavities for deposition of nano-cones, developing high-aspect ratio holes in trackable resists, and as filters for a variety of molecular-sized particles in virtually any liquid or gas by selecting the dielectric material that is compatible with the liquid or gas of interest.
摘要翻译： 用于产生高纵横比（即，远大于直径的长度）的电介质材料中的核轨道的蒸汽蚀刻，已经暴露于高能原子粒子的电介质材料中的孤立的圆柱形孔。 该方法包括清洁被跟踪材料的表面并将清洁的表面暴露于合适蚀刻剂的蒸汽。 独立控制蒸汽和跟踪材料的温度提供了单独改变潜在轨道区域和非轨道材料的蚀刻速率的手段。 通常，跟踪区域以比非跟踪区域更大的速率蚀刻。 此外，通过随后在液体蚀刻剂中浸渍，可以使蒸气蚀刻的孔扩大和平滑。 由气相蚀刻工艺产生的20-1000nm直径的孔可用作用于电镀纳米尺寸丝的模具，用于沉积纳米锥体的蚀刻门腔，在可追踪抗蚀剂中显影高纵横比孔，以及用于 通过选择与感兴趣的液体或气体相容的电介质材料，实际上任何液体或气体中的各种分子大小的颗粒。
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公开(公告)号：US06507033B1
公开(公告)日：2003-01-14
申请号：US09280231
申请日：1999-03-29
IPC分类号： H01J37317
CPC分类号： H01J37/244 , H01J2237/24405 , H01J2237/31701
摘要： An improved Faraday cup array for determining the dose of ions delivered to a substrate during ion implantation and for monitoring the uniformity of the dose delivered to the substrate. The improved Faraday cup array incorporates a variable size ion beam aperture by changing only an insertable plate that defines the aperture without changing the position of the Faraday cups which are positioned for the operation of the largest ion beam aperture. The design enables the dose sensitivity range, typically 1011-1018 ions/cm2 to be extended to below 106 ions/cm2. The insertable plate/aperture arrangement is structurally simple and enables scaling to aperture areas between 750 cm2, and enables ultra-high vacuum (UHV) applications by incorporation of UHV-compatible materials.
摘要翻译： 改进的法拉第杯阵列，用于确定离子注入期间输送到基底的离子的剂量，并用于监测递送至基底的剂量的均匀性。 改进的法拉第杯阵列通过仅改变限定孔径的可插入板而不改变为最大离子束孔径的操作定位的法拉第杯的位置而包括可变尺寸的离子束孔径。 该设计使得剂量敏感性范围通常为1011-1018个离子/ cm 2可以延伸到低于106个离子/ cm 2。 可插入板/孔布置在结构上是简单的，并且能够缩小到<1cm 2和> 750cm 2之间的孔径区域，并且通过结合UHV兼容材料能够实现超高真空（UHV）应用。
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4.发明授权Formation of nanometer-size wires using infiltration into latent nuclear tracks 失效使用渗透到潜在核轨道中形成纳米尺寸的电线公开(公告)号：US06444256B1
公开(公告)日：2002-09-03
申请号：US09441113
申请日：1999-11-17
申请人： Ronald G. Musket , Thomas E. Felter
发明人： Ronald G. Musket , Thomas E. Felter
IPC分类号： B05D512
CPC分类号： H01L21/76838 , H01L21/31155 , H01L2221/1094
摘要： Nanometer-size wires having a cross-sectional dimension of less than 8 nm with controllable lengths and diameters are produced by infiltrating latent nuclear or ion tracks formed in trackable materials with atomic species. The trackable materials and atomic species are essentially insoluble in each other, thus the wires are formed by thermally driven, self-assembly of the atomic species during annealing, or re-crystallization, of the damage in the latent tracks. Unlike conventional ion track lithography, the inventive method does not require etching of the latent tracks.
摘要翻译： 具有可控长度和直径的横截面尺寸小于8nm的纳米尺寸线通过用原子种渗透形成在可跟踪材料中的潜在核或离子轨迹来产生。 可跟踪材料和原子物质基本上彼此不溶，因此在退火或再结晶期间潜在轨迹中的损伤的热驱动，自组装原子物质形成电线。 与传统的离子轨迹光刻不同，本发明的方法不需要蚀刻潜线。
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5.发明授权Process for forming one or more substantially pure layers in substrate material using ion implantation 失效使用离子注入在衬底材料中形成一个或多个基本上纯的层的工艺
公开(公告)号：US4976987A
公开(公告)日：1990-12-11
申请号：US391904
申请日：1989-08-10
CPC分类号： C23C14/5806 , C23C14/48 , C23C14/58 , C23C14/584 , C23C14/5873
摘要： A process is disclosed for forming a substantially pure layer of an implantable element in a substrate material by (a) selecting an implantable element and a substrate material to be implanted which, at the temperatures to be used, have limited mutual solubility in one another and do not form any intermediate phases with one another; (b) implanting a sufficient amount of the implantable element in the substrate material to permit formation of the desired substantially pure layer of the implantable element in the substrate material; and (c) annealing the implanted substrate material to form the desired layer. The annealing step may not be required if the desired layer was formed during the implantation.
摘要翻译： 公开了一种用于通过（a）选择可植入元件和待注入的衬底材料来形成衬底材料中基本上纯的可植入元件层的工艺，所述可植入元件和待使用的衬底材料在相互之间的相互溶解度有限， 不要彼此形成任何中间阶段; （b）将足够数量的可植入元件植入衬底材料中以允许在衬底材料中形成期望的基本上纯的可植入元件层; 和（c）对注入的衬底材料进行退火以形成所需的层。 如果在植入期间形成所需的层，则可能不需要退火步骤。
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公开(公告)号：US5993281A
公开(公告)日：1999-11-30
申请号：US872031
申请日：1997-06-10
申请人： Ronald G. Musket
发明人： Ronald G. Musket
IPC分类号： H01J9/02
CPC分类号： H01J9/025 , H01J2209/0226
摘要： A process for sharpening arrays of field emitter tips of field emission cathodes, such as found in field-emission, flat-panel video displays. The process uses sputtering by high-energy (more than 30 keV) ions incident along or near the longitudinal axis of the field emitter to sharpen the emitter with a taper from the tip or top of the emitter down to the shank of the emitter. The process is particularly applicable to sharpening tips of emitters having cylindrical or similar (e.g., pyramidal) symmetry. The process will sharpen tips down to radii of less than 12 nm with an included angle of about 20 degrees. Because the ions are incident along or near the longitudinal axis of each emitter, the tips of gated arrays can be sharpened by high-energy ion beams rastered over the arrays using standard ion implantation equipment. While the process is particularly applicable for sharpening of arrays of field emitters in field-emission flat-panel displays, it can be effectively utilized in the fabrication of other vacuum microelectronic devices that rely on field emission of electrons.
摘要翻译： 用于锐化场致发射阴极的场发射器尖端的阵列的过程，例如在场致发射，平板显示器中发现的。 该过程使用通过在场发射器的纵轴上或附近入射的高能量（大于30keV）的离子来溅射，以从发射器的尖端或顶部向下到发射体的柄部的锥度来锐化发射器。 该方法特别适用于磨削具有圆柱形或类似（例如，金字塔形）对称性的发射体的尖端。 该过程将尖端锐化为小于12nm的半径，夹角约为20度。 因为离子沿着或靠近每个发射器的纵向轴线入射，所以门控阵列的尖端可以通过使用标准离子注入设备在阵列上被扫描的高能离子束来锐化。 虽然该方法特别适用于在场致发射平板显示器中锐化场致发射体的阵列，但是其可以有效地用于制造依赖于电子场发射的其它真空微电子器件。
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7.发明授权Process for forming one or more substantially pure layers in substrate material using ion implantation 失效使用离子注入在衬底材料中形成一个或多个基本上纯的层的工艺
公开(公告)号：US5124174A
公开(公告)日：1992-06-23
申请号：US625340
申请日：1990-12-11
CPC分类号： C23C14/5806 , C23C14/48 , C23C14/58 , C23C14/584 , C23C14/5873
摘要： A process is disclosed for forming a substantially pure monocrystalline layer of an implantable element in a monocrystalline substrate material by (a) selecting an implantable element and a monocrystalline substrate material to be implanted which, at the temperatures to be used, have limited mutual solubility in one another and do not form any intermediate phases with one another; (b) implanting a sufficient amount of the implantable element in the substrate material to permit formation of the desired substantially pure layer of the implantable element in the substrate material; and (c) annealing the implanted substrate material to form the desired layer. The annealing step may not be required if the desired layer was formed during the implantation.Also disclosed is an article made by the process.
摘要翻译： 公开了一种用于在单晶衬底材料中形成基本上纯的可植入元件的单晶层的工艺，方法是通过（a）选择可植入元件和待植入的单晶衬底材料，其在待使用的温度下具有有限的相互溶解度 彼此之间不形成中间阶段; （b）将足够数量的可植入元件植入衬底材料中以允许在衬底材料中形成期望的基本上纯的可植入元件层; 和（c）对注入的衬底材料进行退火以形成所需的层。 如果在植入期间形成所需的层，则可能不需要退火步骤。 还披露了由该方法制成的文章。
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