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公开(公告)号：US5991837A
公开(公告)日：1999-11-23
申请号：US982573
申请日：1997-12-02
CPC分类号： H05K7/20145 , G06F13/409
摘要： Reversing the orientation of the processors in a dual-processor arrangement enables the overall length of the host bus to be reduced. In addition, less board layers may be required because the number of data and address/control bus crossovers is also reduced. Furthermore, the heat-dissipation surfaces of the processors may be aligned to face one another thereby forming a channel. This makes it more efficient to cool the processors because heat may be drawn away from each processor with a common fluid stream that can be propelled through the channel with a single fluid propeller.
摘要翻译： 以双处理器布置方式颠倒处理器的方向，可以减少主机总线的总长度。 此外，由于数据和地址/控制总线分频器的数量也减少，所以可能需要较少的电路板层。 此外，处理器的散热表面可以彼此对准，从而形成通道。 这使得冷却处理器更有效率，因为可以用可以通过单个流体螺旋桨通过通道推动的公共流体流从每个处理器抽出热量。
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公开(公告)号：US6122695A
公开(公告)日：2000-09-19
申请号：US25722
申请日：1998-02-18
申请人： Jeffrey J. Cronin
发明人： Jeffrey J. Cronin
CPC分类号： H05K1/0246 , G06F13/4086 , H05K7/1431 , H05K1/0231 , H05K1/14 , H05K1/141 , H05K1/142 , H05K2201/044 , H05K2201/10022 , H05K2201/10325 , H05K2201/10704
摘要： A device for terminating a bus configured to have one or more processors coupled thereto. The device comprises a support member having a termination circuit which is coupled to a conductor of the bus when the support member is coupled to the bus. In one embodiment, the support member is coupled between the bus and the processor. In another embodiment, the support member is connected to the bus separately from the processor. The support member may include an auxiliary circuit in addition to the termination circuit which may be used to correct, supply, or update signals transmitted on the bus.
摘要翻译： 一种用于终止被配置为具有与其耦合的一个或多个处理器的总线的设备。 该装置包括支撑构件，该支撑构件具有当支撑构件联接到总线时耦合到总线的导体的终端电路。 在一个实施例中，支撑构件耦合在总线和处理器之间。 在另一个实施例中，支撑构件与处理器分开连接到总线。 除了可用于校正，提供或更新在总线上发送的信号的终端电路之外，支持构件可以包括辅助电路。
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3.发明授权Method and system for terminating write commands in a hub-based memory system 有权用于在基于集线器的存储器系统中终止写入命令的方法和系统公开(公告)号：US07363419B2
公开(公告)日：2008-04-22
申请号：US10857467
申请日：2004-05-28
IPC分类号： G06F12/00
CPC分类号： G06F13/423 , G06F13/1684 , G06F13/4256
摘要： A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.
摘要翻译： 存储器集线器接收下游存储器命令并处理每个接收到的下游存储器命令以确定存储器命令是否包括指向存储器集线器的写入命令。 当写入命令被引导到集线器以开发适于被应用于存储器件的存储器访问信号时，存储器集线器以第一模式工作。 当写入命令不指向集线器以在适于耦合到下游存储器集线器的下游输出端口上提供命令的写入数据时，存储器集线器以第二模式运行。
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公开(公告)号：US6128685A
公开(公告)日：2000-10-03
申请号：US025388
申请日：1998-02-18
申请人： Jeffrey J. Cronin
发明人： Jeffrey J. Cronin
CPC分类号： H05K1/0246 , G06F13/4086 , H05K7/1092 , H05K1/0231 , H05K1/14 , H05K1/141 , H05K1/142 , H05K2201/044 , H05K2201/10022 , H05K2201/10325 , H05K2201/10704
摘要： A method for terminating a bus configured to have one or more processors coupled thereto. The method comprises coupling a support member having a termination circuit thereon to a conductor of the bus. In one embodiment, the support member is connected to the bus separately from the processor. In another embodiment, the support member is coupled between the bus and the processor. The support member may include an auxiliary circuit in addition to the termination circuit and may be used to correct, supply, or update signals transmitted on the bus.
摘要翻译： 一种用于终止被配置为具有与其耦合的一个或多个处理器的总线的方法。 该方法包括将其上具有终端电路的支撑构件连接到总线的导体。 在一个实施例中，支撑构件与处理器分开地连接到总线。 在另一个实施例中，支撑构件耦合在总线和处理器之间。 支持构件除了终端电路之外还可以包括辅助电路，并且可以用于校正，提供或更新在总线上传输的信号。
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5.发明授权Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 有权用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法公开(公告)号：US08694735B2
公开(公告)日：2014-04-08
申请号：US13612490
申请日：2012-09-12
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译： 存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路， 将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。 提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。 在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。
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6.发明申请APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM 有权基于HUB的存储器子系统中的双向数据总线的数据旁路的装置和方法公开(公告)号：US20130007384A1
公开(公告)日：2013-01-03
申请号：US13612490
申请日：2012-09-12
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译： 存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路， 将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。 提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。 在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。
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7.发明申请APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM 有权基于HUB的存储器子系统中的双向数据总线的数据旁路的装置和方法公开(公告)号：US20100287323A1
公开(公告)日：2010-11-11
申请号：US12840007
申请日：2010-07-20
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译： 存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路， 将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。 提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。 在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。
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8.发明授权Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 有权用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法公开(公告)号：US08291173B2
公开(公告)日：2012-10-16
申请号：US12840007
申请日：2010-07-20
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译： 存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路， 将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。 提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。 在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。
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9.发明授权Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 有权用于基于集线器的存储器子系统中的双向数据总线的数据旁路的装置和方法公开(公告)号：US07788451B2
公开(公告)日：2010-08-31
申请号：US10773583
申请日：2004-02-05
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F12/0888 , G06F13/161
摘要： A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
摘要翻译： 存储器集线器包括用于耦合到相应的数据总线的第一和第二链路接口，耦合到第一和第二链路接口的数据路径，以及数据在第一和第二链路接口之间传送的数据路径，并且还包括写入旁路电路， 将数据路径耦合到数据路径上的数据路径，并临时存储写入数据，以允许在暂时存储写入数据时通过数据路径传送读取数据。 提供了一种将数据写入存储器系统中的存储器位置的方法，其包括访问存储器系统中的读取数据，向存储器系统提供写入数据，以及将写入数据耦合到寄存器以进行临时存储。 在提供读取的数据之后，将写入数据重新耦合到存储器总线并写入存储器位置。
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10.发明授权Method and system for terminating write commands in a hub-based memory system 有权用于在基于集线器的存储器系统中终止写入命令的方法和系统公开(公告)号：US07774559B2
公开(公告)日：2010-08-10
申请号：US11895894
申请日：2007-08-27
IPC分类号： G06F12/00
CPC分类号： G06F13/423 , G06F13/1684 , G06F13/4256
摘要： A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.
摘要翻译： 存储器集线器接收下游存储器命令并处理每个接收到的下游存储器命令以确定存储器命令是否包括指向存储器集线器的写入命令。 当写入命令被引导到集线器以开发适于被应用于存储器件的存储器访问信号时，存储器集线器以第一模式工作。 当写入命令不指向集线器以在适于耦合到下游存储器集线器的下游输出端口上提供命令的写入数据时，存储器集线器以第二模式运行。
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