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公开(公告)号：US4723225A
公开(公告)日：1988-02-02
申请号：US786981
申请日：1985-10-15
CPC分类号： G11C16/10
摘要： An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.2 is established at the junction of the second circuit element and the module floating gate transistor. Comparing means compares voltages V.sub.1 and V.sub.2 and adjusts the gate voltage V.sub.3 of the module programming control transistor so as to make the voltage V.sub.2 equal to voltage V.sub.1 and applies voltage V.sub.3 to the gates of the array programming control transistors. Since the transistor in the reference path is both electrically and geometrically the same as that in the second leg across which the voltage developed is compared, and is made by the same process, the current in the second leg will be substantially the same as that in the reference leg. Moreover, since the array floating gate transistors are also made by the same process as is the module floating gate transistor and the programming control and ground select transistors are also identical, by feeding the voltage V.sub.3 to array control transistors substantially the same current will flow through a selected array transistor as flows through both the reference current path and the second current leg.
摘要翻译： 一种具有可编程半导体浮置栅极晶体管阵列的类型的电可编程半导体存储器件，其组合耦合在相关联的源极和漏极线之间，阵列编程控制晶体管和接地选择晶体管，其耦合到每个漏极和源极线 。 编程模式中的每个选择的浮栅晶体管与高电压Vpp和地电位之间的控制和接地选择晶体管串联。 与第一导电电路元件串联的电阻元件建立在电阻元件和电路元件的结处产生电压V1的参考电流。 在第二电流支路中，第二导通电路元件，偏置于导通状态的模块浮栅晶体管和模块控制晶体管都连接在Vpp和地之间，使得在第二电路元件和 模块浮栅晶体管。 比较装置比较电压V1和V2并调节模块编程控制晶体管的栅极电压V3，以使电压V2等于电压V1，并将电压V3施加到阵列编程控制晶体管的栅极。 由于参考路径中的晶体管的电学和几何尺寸与第二支腿相同，因此，通过相同的工艺制造电压，并且通过相同的工艺制造电压，第二支脚中的电流将基本上与 参考腿 此外，由于阵列浮栅晶体管也是通过与模块浮栅晶体管相同的工艺制成的，并且编程控制和接地选择晶体管也相同，通过将电压V3馈送到阵列控制晶体管，基本上相同的电流将流过 所选择的阵列晶体管流过参考电流路径和第二电流支路。
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公开(公告)号：US4722075A
公开(公告)日：1988-01-26
申请号：US786991
申请日：1985-10-15
摘要： An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
摘要翻译： 一种晶体管存储单元的阵列，其中每个单元具有晶体管，接地选择开关和读出放大器耦合开关。 建立电压VBIAS的偏置电压线通过位线晶体管耦合到每个位线，位线晶体管在读取模式期间的栅极至少约为高于VBIAS的电压VT。 类似地，每个晶体管的源极通过其栅极大约约VBIAS的电压VT的源极线晶体管耦合到偏置电压线。 上述布置确保了对于每个未选择的晶体管，晶体管的源极电压将等于其漏极电压，使得所有未选择的晶体管将基本上不导通。
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公开(公告)号：US4740925A
公开(公告)日：1988-04-26
申请号：US786992
申请日：1985-10-15
CPC分类号： G11C29/24
摘要： A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate. In response to a control signal KILLB being applied to both the NAND gate and to the gate of the second selected row, it is possible to use the second selected row to test the first selected row and vice versa.
摘要翻译： 一种制造可编程只读半导体存储器单元的阵列的方法，其包括形成存储器单元的额外行和耦合到其上的对应的额外行栅。 额外的行栅极使能装置被耦合到额外的行栅极，以响应于施加到其上的控制信号KILLT来启用额外的行栅极。 禁用装置耦合到除额外行门以外的第一选定行门，以便响应于施加到其上的控制信号KILLT来禁用所选择的行门。 禁止装置耦合到除了额外行门以外的第一选择的行门，以便响应于施加到其上的控制信号KILL而禁用所选择的行门。 NAND门可以用额外的行门形成，以允许对应于第二选定行的存储器单元的第二组信号使第二选择的行门能够被执行。 禁用装置耦合到除了额外的行门之外的第二选择的行门。 响应于控制信号KILLB被施加到NAND门和第二选择行的栅极，可以使用第二选定行来测试第一选定行，反之亦然。
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公开(公告)号：US4802121A
公开(公告)日：1989-01-31
申请号：US869471
申请日：1986-06-02
CPC分类号： G11C16/0491
摘要： A memory array having two separate sets of parallel bit lines, and a word line intersecting the sets of bit lines. The memory cells are floating-gate MOS transistors having gates coupled to associated ones of the word lines and source-to-drain paths connected between alternating ones of the sets of bit lines and ground lines.
摘要翻译： 具有两组分离的并行位线的存储器阵列和与位线组相交的字线。 存储器单元是浮栅MOS晶体管，其具有耦合到字线中的相关联的栅极和连接在位线组和接地线中的交替的位置之间的源极到漏极路径的栅极。
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