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公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译： 一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。 由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。 标记为最低优先级可重定向的中断根据任务优先级信息重定向。 提供对XTPR事务的支持以更新XTPR寄存器。 提供XTPR更新事务和重定向中断的优先顺序。
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公开(公告)号：US06499085B2
公开(公告)日：2002-12-24
申请号：US09752846
申请日：2000-12-29
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/0835
摘要： A system is described for servicing a full cache line in response to a partial cache line request. The system includes a storage to store at least one cache line, a hit/miss detector, and a data mover. The hit/miss detector receives a partial cache line read request from a requesting agent and dispatches a fetch request to a memory device to fetch a full cache line data that contains data requested in the partial cache line read request from the requesting agent. The data mover loads the storage with the full cache line data returned from the memory device and forwards a portion of the full cache line data requested by the requesting agent. If data specified in a subsequent partial cache line request from the requesting agent is contained within the full cache line data specified in the previously dispatched fetch request, the hit/miss detector will send a command to the data mover to forward another portion of the full cache line data stored in the storage to the requesting agent. In one embodiment, the system also includes a write combining logic to combine two or more consecutive write requests that meet defined conditions into a single write request.
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公开(公告)号：US07610611B2
公开(公告)日：2009-10-27
申请号：US10666077
申请日：2003-09-19
CPC分类号： G06F12/1441
摘要： A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.
摘要翻译： 已经公开了优先地址解码器。 优先地址解码器的一个实施例包括第一比较器，用于将数据的目的地设备地址与与第一设备相关联的第一地址范围和耦合到第一比较器的第二比较器进行比较，以将目的地设备地址与相关联的第二地址范围进行比较 利用第二设备，其中响应于第一比较器的第一输出和第二比较器的第二输出将数据发送到第二设备。
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公开(公告)号：US20050086508A1
公开(公告)日：2005-04-21
申请号：US10666077
申请日：2003-09-19
申请人： Douglas Moran , Satish Acharya , Zohar Bogln , Sean Galloway
发明人： Douglas Moran , Satish Acharya , Zohar Bogln , Sean Galloway
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.
摘要翻译： 已经公开了优先地址解码器。 优先地址解码器的一个实施例包括第一比较器，用于将数据的目的地设备地址与与第一设备相关联的第一地址范围和耦合到第一比较器的第二比较器进行比较，以将目的地设备地址与相关联的第二地址范围进行比较 利用第二设备，其中响应于第一比较器的第一输出和第二比较器的第二输出将数据发送到第二设备。
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