公开(公告)号：US06055584A

公开(公告)日：2000-04-25

申请号：US975540

申请日：1997-11-20

申请人： Jeffrey Todd Bridges ,  Edward Hammond Green, III ,  Richard Gerard Hofmann ,  David Otero ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

发明人： Jeffrey Todd Bridges ,  Edward Hammond Green, III ,  Richard Gerard Hofmann ,  David Otero ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F13/28

摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.

摘要翻译： 提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。 从总线控制器还耦合到存储器单元。 存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。 从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。 在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。 这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

公开(公告)号：US20060190871A1

公开(公告)日：2006-08-24

申请号：US11053220

申请日：2005-02-08

申请人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  David Otero ,  Chad Winemiller

发明人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  David Otero ,  Chad Winemiller

IPC分类号： G06F17/50

CPC分类号： G01R31/318314

摘要： Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.

摘要翻译： 公开了用于管理可参数化设计的功能验证的方法，系统和媒体。 实施例包括具有测试台配置模块的系统，该测试台配置模块适于配置测试台，测试台具有测试台信号，以及具有多个通用设计端口的一个或多个实例组件，其中测试台信号被连接到多个端口。 测试台还可以具有基于芯片特定版本的设计的一个或多个实例化的特殊组件，其中特殊组件被连接到与通用设计相同的端口。 该系统还可以包括功能验证管理器，其通过组件模块观察测试台中的值并且基于所观察到的值自动配置验证环境，包括在不同层次结构中自动插入检查器。 在一些实施例中，测试台可以是VHDL或Verilog测试台。

公开(公告)号：US07237210B2

公开(公告)日：2007-06-26

申请号：US11053220

申请日：2005-02-08

申请人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  David Otero ,  Chad Everett Winemiller

发明人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  David Otero ,  Chad Everett Winemiller

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G01R31/318314

摘要： Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.

摘要翻译： 公开了用于管理可参数化设计的功能验证的方法，系统和媒体。 实施例包括具有测试台配置模块的系统，该测试台配置模块适于配置测试台，测试台具有测试台信号，以及具有多个通用设计端口的一个或多个实例组件，其中测试台信号被连接到多个端口。 测试台还可以具有基于芯片特定版本的设计的一个或多个实例化的特殊组件，其中特殊组件被连接到与通用设计相同的端口。 该系统还可以包括功能验证管理器，其通过组件模块观察测试台中的值并且基于所观察到的值自动配置验证环境，包括在不同层次结构中自动插入检查器。 在一些实施例中，测试台可以是VHDL或Verilog测试台。