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公开(公告)号：US08298881B2
公开(公告)日：2012-10-30
申请号：US12824293
申请日：2010-06-28
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。
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公开(公告)号：US08829625B2
公开(公告)日：2014-09-09
申请号：US13572114
申请日：2012-08-10
IPC分类号： H01L27/088
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源极和漏极区域。
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公开(公告)号：US20120305886A1
公开(公告)日：2012-12-06
申请号：US13572114
申请日：2012-08-10
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源极和漏极区域。
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公开(公告)号：US20110315950A1
公开(公告)日：2011-12-29
申请号：US12824293
申请日：2010-06-28
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。
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公开(公告)号：US20100252810A1
公开(公告)日：2010-10-07
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/41 , H01L21/306 , H01L21/302
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。
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公开(公告)号：US08445948B2
公开(公告)日：2013-05-21
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。
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公开(公告)号：US20110006367A1
公开(公告)日：2011-01-13
申请号：US12886139
申请日：2010-09-20
申请人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C.M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L27/12
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。
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公开(公告)号：US07816275B1
公开(公告)日：2010-10-19
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译： 提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。 在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。 使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。 在另一个实施例中，使用封装/钝化层。 在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。
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公开(公告)号：US20200165340A1
公开(公告)日：2020-05-28
申请号：US16486150
申请日：2017-02-16
发明人： Ying Zhang
IPC分类号： C07K16/28 , A61K39/395 , A61P35/00 , A61K31/454
摘要： Anti-programmed death-ligand 1 (PD-L1) antibodies, methods of using the same, therapeutic compositions thereof, and uses thereof in upregulating cell-mediated immune responses and treating T cell dysfunctional disorders are provided. The use of the anti-PD-L1 antibody as a diagnostic agent in vitro is also provided.
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公开(公告)号：US20200062847A1
公开(公告)日：2020-02-27
申请号：US16488667
申请日：2017-03-04
发明人： Ying Zhang
IPC分类号： C07K16/28
摘要： Provided are monoclonal antibody, particularly rabbit recombinant antibody, which specifically binds to human PD-1 with biological functions and super high affinity, and methods of use. In various embodiments, the antibodies are fully humanized antibodies that bind to human PD-1. Nucleic acid molecules encoding the antibodies and methods for expressing the antibodies are also provided. In some embodiments, the antibodies are useful for inhibiting or neutralizing PD-1 activity, thus providing a means of treating, preventing and/or diagnosing a disease or disorder such as cancer or a viral infection.
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