利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.012 秒)

    METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS
    1.
    发明申请
    METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
    形成改善间隔物的方法，用于改善耐压氮化膜的有效性

    公开(公告)号：US20080182372A1

    公开(公告)日：2008-07-31

    申请号：US11669645

    申请日：2007-01-31

    申请人： Joyce C. Liu ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

    发明人： Joyce C. Liu ,  Hongwen Yan ,  Qingyun Yang ,  Ying Zhang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.

    摘要翻译： 形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

    Method to controllably form notched polysilicon gate structures
    5.
    发明授权
    Method to controllably form notched polysilicon gate structures 失效
    可控地形成切口多晶硅栅极结构的方法

    公开(公告)号：US06541320B2

    公开(公告)日：2003-04-01

    申请号：US09928210

    申请日：2001-08-10

    申请人： Jeffrey Brown ,  Richard Wise ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

    发明人： Jeffrey Brown ,  Richard Wise ,  Hongwen Yan ,  Qingyun Yang ,  Chienfan Yu

    IPC分类号： H01L21336

    CPC分类号： H01L21/32137 ,  H01L21/28114 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/42376

    摘要： A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.

    摘要翻译： 一种用于形成在栅极介电层上具有栅极导体层的缺口栅极结构的方法和结构。 栅极导体层具有第一厚度。 本发明的方法包括在栅极导体层上图案化掩模，在未被掩模保护的区域中将栅极导体层蚀刻到减小的厚度（减小的厚度小于第一厚度），在栅极导体上沉积钝化膜 蚀刻钝化膜以从栅极导体层的水平部分去除钝化膜（使用各向异性蚀刻），选择性地蚀刻栅极导体层以从不受掩模或钝化膜保护的所有区域去除栅极导体层 。 这在栅极导体与栅极介电层相遇的拐角处形成栅极导体层内的底切凹口。 钝化膜包括含C的膜，含Si膜，含Si-C的膜或其组合。

    Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure
    6.
    发明申请
    Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure 有权
    去除栅极结构侧壁上高K电介质层的方法

    公开(公告)号：US20120256278A1

    公开(公告)日：2012-10-11

    申请号：US13080084

    申请日：2011-04-05

    申请人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

    发明人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

    摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

    摘要翻译： 一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。 高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。 半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。

    REPLACEMENT SOURCE/DRAIN FOR 3D CMOS TRANSISTORS
    9.
    发明申请
    REPLACEMENT SOURCE/DRAIN FOR 3D CMOS TRANSISTORS 有权
    替代3D CMOS晶体管的源/漏

    公开(公告)号：US20140070316A1

    公开(公告)日：2014-03-13

    申请号：US13614062

    申请日：2012-09-13

    申请人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

    发明人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7848

    摘要： A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

    摘要翻译： 形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。 栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。 形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。 通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。 第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

    Method of removing high-K dielectric layer on sidewalls of gate structure
    10.
    发明授权
    Method of removing high-K dielectric layer on sidewalls of gate structure 有权
    去除栅极结构侧壁上的高K电介质层的方法

    公开(公告)号：US08481389B2

    公开(公告)日：2013-07-09

    申请号：US13080084

    申请日：2011-04-05

    申请人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

    发明人： Ying Zhang ,  Qingyun Yang ,  Hongwen Yan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

    摘要： A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

    摘要翻译： 一种半导体结构，以及形成半导体结构的方法，其包括半导体衬底上的栅极结构，其中栅极结构包括栅极导体和高k栅极电介质层。 高k栅极电介质层与栅极导体的基极接触并且存在于栅极导体的侧壁上，尺寸小于栅极结构的高度的1/4。 半导体结构还包括在栅极结构的相对侧上存在于半导体衬底中的源极区和漏极区。