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    Embedding of dynamic circuits in a static environment
    1.
    发明授权
    Embedding of dynamic circuits in a static environment 失效
    在静态环境中嵌入动态电路

    公开(公告)号：US06518793B2

    公开(公告)日：2003-02-11

    申请号：US09815355

    申请日：2001-03-22

    申请人： Jens Leenstra ,  Hans-Werner Tast ,  Dieter Wendel ,  Peter Hofstee

    发明人： Jens Leenstra ,  Hans-Werner Tast ,  Dieter Wendel ,  Peter Hofstee

    IPC分类号： H03K1900

    CPC分类号： G01R31/318577 ,  G01R31/318583 ,  G01R31/318586

    摘要： The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

    摘要翻译： 本发明涉及关于逻辑和定时验证的改进，作为包括在静态环境中嵌入动态逻辑电路的硬件电路的可测试性。 包含动态逻辑电路的时钟宏在锁存器的输入和输出两端都被限制，保持输入和输出信号到时钟宏。 静态输入信号用波形格式化装置处理，以产生可用于动态逻辑电路的评估的波形，并且动态逻辑输出信号通过设置/复位锁存器转换回静态信号，使得它可以 被静态嵌入电路的时钟信号锁存。 因此，芯片设计中的定时和逻辑仿真分析方法可以与静态逻辑中使用的分析方法相同，特别是可以使用LSSD测试方法。

    Electronic circuit for implementing a permutation operation
    3.
    发明申请
    Electronic circuit for implementing a permutation operation 失效
    用于实现置换操作的电子电路

    公开(公告)号：US20070011220A1

    公开(公告)日：2007-01-11

    申请号：US11390791

    申请日：2006-03-28

    申请人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Mevergnies ,  Hans-Werner Tast

    发明人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Mevergnies ,  Hans-Werner Tast

    IPC分类号： G06F17/15

    CPC分类号： G06F7/766

    摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.

    摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

    Electronic circuit for implementing a permutation operation
    4.
    发明授权
    Electronic circuit for implementing a permutation operation 失效
    用于实现置换操作的电子电路

    公开(公告)号：US07783690B2

    公开(公告)日：2010-08-24

    申请号：US11390791

    申请日：2006-03-28

    申请人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Neve de Mevergnies ,  Hans-Werner Tast

    发明人： Jens Leenstra ,  Nicolas Maeding ,  Amaury Neve de Mevergnies ,  Hans-Werner Tast

    IPC分类号： G06F15/00

    CPC分类号： G06F7/766

    摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.

    摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

    System and method for scanning sequential logic elements
    6.
    发明授权
    System and method for scanning sequential logic elements 有权
    用于扫描顺序逻辑元件的系统和方法

    公开(公告)号：US07913132B2

    公开(公告)日：2011-03-22

    申请号：US12273985

    申请日：2008-11-19

    申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

    发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318536

    摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

    摘要翻译： 公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

    Read/write alignment scheme for port reduction of multi-port SRAM cells
    8.
    发明授权
    Read/write alignment scheme for port reduction of multi-port SRAM cells 失效
    用于多端口SRAM单元端口缩减的读/写对准方案

    公开(公告)号：US06785781B2

    公开(公告)日：2004-08-31

    申请号：US09825072

    申请日：2001-04-03

    申请人： Jens Leenstra ,  Juergen Pille ,  Rolf Sautter ,  Dieter Wendel

    发明人： Jens Leenstra ,  Juergen Pille ,  Rolf Sautter ,  Dieter Wendel

    IPC分类号： G06F1200

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G11C8/16

    摘要： A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

    摘要翻译： 根据本发明，通过将输入端口的数量和输出端口的数量减少到同时预期的阵列访问的数量n，可以节省相当多的面积。 当利用关于阵列利用的一些知识时，可以实现端口的显着减少，从而实现非常相关的区域保存：阵列访问将由最多k个特定组的并发访问执行。 一组由多个阵列访问定义，每次访问至多一次访问同一个端口。 然后，为了读取，读取结果根据简单的重新布线方案对齐到相应的读取请求者，而对于写入，根据相同或相似的方案在阵列访问之前进行对齐。

    Method and system for pipeline reduction
    9.
    发明授权
    Method and system for pipeline reduction 有权
    减少管道的方法和系统

    公开(公告)号：US07844799B2

    公开(公告)日：2010-11-30

    申请号：US09683383

    申请日：2001-12-20

    申请人： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

    发明人： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

    IPC分类号： G06F9/30 ,  G06F9/34

    CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

    摘要： A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.

    摘要翻译： 一种用于操作具有增加的管道长度的高频无序处理器的方法和系统。 公开了一种新方案，通过对指令的所谓“不依赖”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于指令。 因此，管道的一个或多个阶段被绕过。

    Rename finish conflict detection and recovery
    10.
    发明授权
    Rename finish conflict detection and recovery 失效
    重新完成冲突检测和恢复

    公开(公告)号：US06829699B2

    公开(公告)日：2004-12-07

    申请号：US09683391

    申请日：2001-12-20

    申请人： Jens Leenstra ,  Dieter Wendel

    发明人： Jens Leenstra ,  Dieter Wendel

    IPC分类号： G06F938

    CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： An improved method and system for operating an out of order processor at a high frequency enabled by an increased pipeline length. It is proposed to shorten the pipeline by a considerable number of stages by accepting that a write after read conflict may occur, when directly after renaming, during the “read ROB” pipeline stage, all the information (tag, validity and data) is read from an Reorder Buffer ROB entry, and is next written, in a following pipeline stage “write RS”, into a reservation station (RS) entry. In order to assure the correctness of processing in particular in cases of dependencies, e.g., write after read conflicts a separate inventional add in logic covers these cases. The logic detects the write after read conflict case of an Instructional Execution Unit (IEU) writing into the particular entry that is selected by the renaming logic during “read ROB”. Then, a separate issue process selects the entries for which a conflict is reported and writes the data into the respective entry of the RS. This increases performance because those conflict cases are rather seldom compared to the broad majority of instructions to be found in a statistically determined average instruction flow.

    摘要翻译： 一种改进的方法和系统，用于通过增加的流水线长度在高频下操作无序处理器。 建议通过接受在读取冲突之后写入，直接在重命名之后，在“读取ROB”流水线阶段期间，可以读取所有信息（标签，有效性和数据），缩短流水线 来自重排序缓冲器ROB条目，并且在下一个流水线级“写入RS”中被写入保留站（RS）条目。 为了确保处理的正确性，特别是在依赖性的情况下，例如在读取冲突之后写入，单独的发明逻辑将覆盖这些情况。 该逻辑检测指令执行单元（IEU）写入读写冲突之后的写入到在“读取ROB”期间由重命名逻辑选择的特定条目。 然后，单独的问题过程选择报告冲突的条目，并将数据写入RS的相应条目。 这增加了性能，因为这些冲突案例与在统计确定的平均指令流程中找到的大多数指令相比很少。