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    Composition for high strength loose tube type fiber optic cable with excellent flexibility and impact resistance
    1.
    发明授权
    Composition for high strength loose tube type fiber optic cable with excellent flexibility and impact resistance 有权
    高强度松套管型光缆的组成，具有优良的柔韧性和抗冲击性

    公开(公告)号：US08909015B2

    公开(公告)日：2014-12-09

    申请号：US13551944

    申请日：2012-07-18

    申请人： Jeong-Eun Lim ,  Yu-Hyoung Lee ,  Gi-Joon Nam

    发明人： Jeong-Eun Lim ,  Yu-Hyoung Lee ,  Gi-Joon Nam

    IPC分类号： G02B6/44

    CPC分类号： G02B6/443 ,  G02B6/441 ,  G02B6/4494 ,  C08F210/06 ,  C08F210/16 ,  C08F2500/12

    摘要： Disclosed is a composition for a high strength loose tube type fiber optic cable with excellent flexibility and excellent impact resistance, which includes a polypropylene-polyethylene copolymer having a melt flow index (MFI) of 1.1 g/10 minutes to 3.0 g/10 minutes at 230° C. and a flexural modulus of 10,000 to 23,000 kg/cm2. A fiber optic cable including a loose tube formed with the composition for a high strength loose tube type fiber optic cable has excellent flexibility and impact resistance as well as excellent appearance.

    摘要翻译： 公开了一种具有优异柔软性和优异抗冲击性的高强度松套管式光纤电缆用组合物，其包括熔融流动指数（MFI）为1.1g / 10分钟至3.0g / 10分钟的聚丙烯 - 聚乙烯共聚物 230℃，挠曲模量为10,000〜23,000kg / cm 2。 包含由高强度松套管式光纤电缆组合物形成的松套管的光缆具有优异的柔韧性和抗冲击性以及出色的外观。

    Scheduling for parallel processing of regionally-constrained placement problem
    2.
    发明授权
    Scheduling for parallel processing of regionally-constrained placement problem 有权

    公开(公告)号：US08578315B2

    公开(公告)日：2013-11-05

    申请号：US13550957

    申请日：2012-07-17

    申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

    发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G06F9/5066

    摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

    Multi-patterning lithography aware cell placement in integrated circuit design
    3.
    发明授权
    Multi-patterning lithography aware cell placement in integrated circuit design 失效
    集成电路设计中的多图案化光刻感知单元放置

    公开(公告)号：US08495548B2

    公开(公告)日：2013-07-23

    申请号：US13248711

    申请日：2011-09-29

    申请人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

    发明人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

    摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。

    Post-placement cell shifting
    4.
    发明授权
    Post-placement cell shifting 失效
    放置后细胞转移

    公开(公告)号：US08495534B2

    公开(公告)日：2013-07-23

    申请号：US12796550

    申请日：2010-06-08

    申请人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

    摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

    Detailed routability by cell placement
    5.
    发明授权
    Detailed routability by cell placement 有权
    细胞放置的详细路线

    公开(公告)号：US08347257B2

    公开(公告)日：2013-01-01

    申请号：US12796501

    申请日：2010-06-08

    申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

    摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

    ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION
    6.
    发明申请
    ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION 失效
    门锁延迟计算的精度针脚模式

    公开(公告)号：US20120324409A1

    公开(公告)日：2012-12-20

    申请号：US13162806

    申请日：2011-06-17

    申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

    发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

    摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

    摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

    WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN
    7.
    发明申请
    WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN 审中-公开
    电路设计中的创新和保存

    公开(公告)号：US20120297355A1

    公开(公告)日：2012-11-22

    申请号：US13112098

    申请日：2011-05-20

    申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod Alexander Roy ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.

    摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。 通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。 将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。 虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。 确定设计是否改进。 当设计没有改进时，创建最终的布局解决方案。

    ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION-CONSTRAINED OBJECTS
    8.
    发明申请
    ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION-CONSTRAINED OBJECTS 失效
    具有部分约束对象的电子设计自动化对象放置

    公开(公告)号：US20120054708A1

    公开(公告)日：2012-03-01

    申请号：US12870624

    申请日：2010-08-27

    申请人： Charles J. Alpert ,  John L. McCann ,  Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  John L. McCann ,  Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.

    摘要翻译： 全局放置器接收多个区域，每个区域占据设计区域的子区域。 接收多个移动对象，每个移动对象与一个区域相关联。 全局放置器接收多个无约束对象，每个无约束对象与无区域相关联。 全局放置器接收公差，其中放置公差将至少一个区域的冠状边缘定义。 全局放置器最初放置多个移动对象和非约束对象。 全局排列器迭代对象而不偏好区域属性来选择对象，其中对象由多个移动对象和多个无约束对象组成。 全局置位器确定移动对象是否在与移动对象相关联的区域的公差范围内。

    POST-PLACEMENT CELL SHIFTING
    9.
    发明申请
    POST-PLACEMENT CELL SHIFTING 失效
    后置放电细胞移位

    公开(公告)号：US20110302544A1

    公开(公告)日：2011-12-08

    申请号：US12796550

    申请日：2010-06-08

    申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

    摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。