公开(公告)号：US20070072319A1

公开(公告)日：2007-03-29

申请号：US11559317

申请日：2006-11-13

Applicant: Jeong-Hoon AHN ,  Kyungtae LEE ,  Mu-Kyung JUNG ,  Yong-Jun LEE

Inventor： Jeong-Hoon AHN ,  Kyungtae LEE ,  Mu-Kyung JUNG ,  Yong-Jun LEE

IPC: H01L21/66 ,  H01L21/331 ,  G01R31/26

CPC classification number: H01L28/55 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1085 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US20110222330A1

公开(公告)日：2011-09-15

申请号：US13032848

申请日：2011-02-23

Applicant: Yong-Jun LEE ,  Kwang Jin LEE ,  Joon Min PARK ,  Huik Won SEO

Inventor： Yong-Jun LEE ,  Kwang Jin LEE ,  Joon Min PARK ,  Huik Won SEO

IPC: G11C17/00 ,  G11C11/00

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0059 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract translation: 非易失性存储器件包括一次性可编程（OTP）锁定位寄存器。 非易失性存储器件包括可变电阻存储单元阵列，其包括存储数据的OTP块和存储指示数据是否可更改的OTP锁定状态信息的寄存器。 寄存器包括可变存储单元。 OTP锁定状态信息的初始值被设置为程序保护状态。

公开(公告)号：US20100124105A1

公开(公告)日：2010-05-20

申请号：US12693005

申请日：2010-01-25

Applicant: Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI ,  Yong-Jun LEE ,  Hye-Jin KIM

Inventor： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI ,  Yong-Jun LEE ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C11/005 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C16/0483 ,  G11C2013/0078 ,  G11C2213/71

Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。