公开(公告)号：US20120187994A1

公开(公告)日：2012-07-26

申请号：US13011716

申请日：2011-01-21

申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

IPC分类号： H03K5/00

CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

公开(公告)号：US08854098B2

公开(公告)日：2014-10-07

申请号：US13011716

申请日：2011-01-21

申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

IPC分类号： H03H11/16 ,  H03D7/14 ,  H03D7/16 ,  H03L7/081 ,  H04L27/36 ,  H04L27/38

CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

公开(公告)号：US6040722A

公开(公告)日：2000-03-21

申请号：US71518

申请日：1998-05-01

申请人： Sang-oh Lee

发明人： Sang-oh Lee

IPC分类号： G11C11/407 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/22

摘要： A power-on reset circuit is provided for generating a power-on reset signal for sequential logics or memory devices as a power supply potential is applied initially. The power-on reset circuit is provided in the same chip as the sequential logics, and generates the signal after an adjustable time interval. The power-on reset circuit includes an oscillator for generating a clock signal, and a counter for counting pulses of the clock signal from when the power supply potential is applied. The time interval is adjusted by loading a preset data value in the counter, which thus outputs a CTR signal when the counted pulses become equal in number to the preset number. A combinational logic circuit resets the counter when the power supply potential is initially applied, and also generates a power-on reset signal when the counter outputs the CTR signal. The power on reset signal further disables the counter, so that the CTR signal is maintained.

摘要翻译： 提供上电复位电路，用于在初始应用电源电位时产生用于顺序逻辑或存储器件的上电复位信号。 上电复位电路设置在与顺序逻辑相同的芯片中，并在可调整的时间间隔后生成信号。 上电复位电路包括用于产生时钟信号的振荡器和用于对来自施加电源电位的时钟信号的脉冲进行计数的计数器。 通过在计数器中加载预设数据值来调整时间间隔，当计数脉冲数量等于预设数量时，输出CTR信号。 组合逻辑电路在最初施加电源电位时复位计数器，并且当计数器输出CTR信号时也产生上电复位信号。 上电复位信号进一步禁止计数器，以保持CTR信号。