公开(公告)号：US07091540B2

公开(公告)日：2006-08-15

申请号：US10682492

申请日：2003-10-10

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L27/108

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US20050218458A1

公开(公告)日：2005-10-06

申请号：US11141312

申请日：2005-06-01

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US07211482B2

公开(公告)日：2007-05-01

申请号：US11141312

申请日：2005-06-01

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/336 ,  H01L21/8228

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US20070069265A1

公开(公告)日：2007-03-29

申请号：US11503130

申请日：2006-08-14

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L29/94

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US20060027869A1

公开(公告)日：2006-02-09

申请号：US11246106

申请日：2005-10-11

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L29/66787

摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

摘要翻译： 垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极 所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极， 源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

公开(公告)号：US07872290B2

公开(公告)日：2011-01-18

申请号：US11503130

申请日：2006-08-14

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L27/108

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

公开(公告)号：US07262462B2

公开(公告)日：2007-08-28

申请号：US11246106

申请日：2005-10-11

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L29/76

CPC分类号： H01L29/78696 ,  H01L29/66787

摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

摘要翻译： 垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极 所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极， 源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

公开(公告)号：US20050017289A1

公开(公告)日：2005-01-27

申请号：US10759239

申请日：2004-01-20

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66787 ,  H01L29/42384 ,  H01L29/78696

摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

公开(公告)号：US06960507B2

公开(公告)日：2005-11-01

申请号：US10759239

申请日：2004-01-20

申请人： Ji-Young Kim ,  Jin-Jun Park

发明人： Ji-Young Kim ,  Jin-Jun Park

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66787 ,  H01L29/42384 ,  H01L29/78696

摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.

摘要翻译： 垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极 所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极， 源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

公开(公告)号：US07663902B2

公开(公告)日：2010-02-16

申请号：US11726867

申请日：2007-03-23

申请人： Jin-Jun Park

发明人： Jin-Jun Park

IPC分类号： G11C5/06

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  H01L27/10 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/943 ,  H01L2924/00

摘要： A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension; and a bit line insulated from the plurality of word lines, intersecting the plurality of word lines and extending in a second direction of extension, a transition electrode portion of the bit line positioned in the gap and spaced apart from the plurality of word lines by a predetermined distance, the transition electrode portion of the bit line configured and arranged to be bent toward any one of the plurality of word lines in response to an electrical signal applied to at least one of the plurality of word lines.

摘要翻译： 存储器件及其制造方法提供能够增加或最大化微结构器件的性能的器件。 该装置包括：多个字线，其间形成有间隙，并沿着第一延伸方向彼此平行延伸; 以及与所述多个字线绝缘的位线，与所述多个字线相交并且沿第二延伸方向延伸，所述位线的过渡电极部分位于所述间隙中并与所述多个字线间隔开一个 所述位线的过渡电极部分被配置和布置为响应于施加到所述多个字线中的至少一个字线的电信号而朝着所述多个字线中的任何一个字线弯曲。