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    Read and write aware cache with a read portion and a write portion of a tag and status array
    3.
    发明授权
    Read and write aware cache with a read portion and a write portion of a tag and status array 有权
    具有读取部分和标签和状态数组的写入部分的读写感知高速缓存

    公开(公告)号：US08843705B2

    公开(公告)日：2014-09-23

    申请号：US13572916

    申请日：2012-08-13

    申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

    摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

    摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

    Read and write aware cache storing cache lines in a read-often portion and a write-often portion
    4.
    发明授权
    Read and write aware cache storing cache lines in a read-often portion and a write-often portion 失效
    将读写缓存存储在经常阅读的部分和经常写入的部分中

    公开(公告)号：US08271729B2

    公开(公告)日：2012-09-18

    申请号：US12562242

    申请日：2009-09-18

    申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

    摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

    摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

    Read and Write Aware Cache
    5.
    发明申请
    Read and Write Aware Cache 失效
    读写写入缓存

    公开(公告)号：US20110072214A1

    公开(公告)日：2011-03-24

    申请号：US12562242

    申请日：2009-09-18

    申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

    摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

    摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

    Read and Write Aware Cache
    6.
    发明申请
    Read and Write Aware Cache 有权
    读写写入缓存

    公开(公告)号：US20120311265A1

    公开(公告)日：2012-12-06

    申请号：US13572916

    申请日：2012-08-13

    申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

    摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement polity. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is place in one of the closer banks. The size ration between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

    摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替代策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存线位于其中一个较近的银行。 常读区域和常写区域之间的大小比例可能是静态或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

    Address translation through an intermediate address space
    7.
    发明授权
    Address translation through an intermediate address space 有权
    通过中间地址空间进行地址转换

    公开(公告)号：US08966219B2

    公开(公告)日：2015-02-24

    申请号：US11928125

    申请日：2007-10-30

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1063 ,  G06F12/1072

    摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

    摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。

    Fine Grained Cache Allocation
    8.
    发明申请
    Fine Grained Cache Allocation 有权
    细粒度缓存分配

    公开(公告)号：US20110022773A1

    公开(公告)日：2011-01-27

    申请号：US12509752

    申请日：2009-07-27

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

    摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

    摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

    Fine grained cache allocation
    9.
    发明授权
    Fine grained cache allocation 有权
    细粒度缓存分配

    公开(公告)号：US08543769B2

    公开(公告)日：2013-09-24

    申请号：US12509752

    申请日：2009-07-27

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

    摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

    摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

    Data Reorganization through Hardware-Supported Intermediate Addresses
    10.
    发明申请
    Data Reorganization through Hardware-Supported Intermediate Addresses 审中-公开
    通过硬件支持的中间地址进行数据重组

    公开(公告)号：US20110238946A1

    公开(公告)日：2011-09-29

    申请号：US12730285

    申请日：2010-03-24

    申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1072 ,  G06F12/0207 ,  G06F12/0292 ,  G06F12/0864

    摘要： A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor).

    摘要翻译： 公开了一种用于提高缓存存储器系统中稀疏存储的数据项的存储器访问的性能和效率的虚拟地址方案。 在本发明的优选实施例中，特殊地址转换单元用于将实际存储器中的不连续地址集合转换为“中间地址空间”中的连续地址块。该中间地址空间是虚拟的或“虚拟的 “地址空间，但是与应用程序可见的虚拟地址空间是区别的，并且在用户级存储器操作中，由应用程序看到/操纵的有效地址由用于存储器高速缓存的附加地址转换单元转换成中间地址。 该方案允许存储器中的不连续的数据项被组合成连续的高速缓存行，以便更有效的高速缓存/访问（由于从处理器的角度看，数据的空间接近）。