公开(公告)号：US08966219B2

公开(公告)日：2015-02-24

申请号：US11928125

申请日：2007-10-30

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/10

CPC分类号： G06F12/1063 ,  G06F12/1072

摘要： In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

摘要翻译： 在能够同时执行多个硬件执行线程的数据处理系统中，处理单元中的中间地址转换单元将存储器访问的有效地址转换为中间地址。 使用中间地址访问高速缓冲存储器。 响应于高速缓冲存储器中的缺失，中间地址被实现地址转换单元转换成实地址，该单元执行多个硬件执行线程的地址转换。 使用实际地址访问系统内存。

公开(公告)号：US08843705B2

公开(公告)日：2014-09-23

申请号：US13572916

申请日：2012-08-13

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

公开(公告)号：US20110022773A1

公开(公告)日：2011-01-27

申请号：US12509752

申请日：2009-07-27

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

公开(公告)号：US08543769B2

公开(公告)日：2013-09-24

申请号：US12509752

申请日：2009-07-27

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/126 ,  Y02D10/13

摘要： A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

摘要翻译： 在虚拟机监视器中提供了用于共享高速缓存中的细粒度高速缓存分配的机制。 该机制将高速缓存标签分成最高有效位（MSB）部分和最低有效位（LSB）部分。 标签的MSB部分在一组中的高速缓存行之间共享。 标签的LSB部分是私有的，每个缓存行一个。 该机制允许软件将缓存中的标签的MSB部分设置为分配高速缓存行集合。 高速缓存控制器基于标签的MSB部分来确定高速缓存行是否被锁定。

公开(公告)号：US20110238946A1

公开(公告)日：2011-09-29

申请号：US12730285

申请日：2010-03-24

申请人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/10

CPC分类号： G06F12/1072 ,  G06F12/0207 ,  G06F12/0292 ,  G06F12/0864

摘要： A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor).

摘要翻译： 公开了一种用于提高缓存存储器系统中稀疏存储的数据项的存储器访问的性能和效率的虚拟地址方案。 在本发明的优选实施例中，特殊地址转换单元用于将实际存储器中的不连续地址集合转换为“中间地址空间”中的连续地址块。该中间地址空间是虚拟的或“虚拟的 “地址空间，但是与应用程序可见的虚拟地址空间是区别的，并且在用户级存储器操作中，由应用程序看到/操纵的有效地址由用于存储器高速缓存的附加地址转换单元转换成中间地址。 该方案允许存储器中的不连续的数据项被组合成连续的高速缓存行，以便更有效的高速缓存/访问（由于从处理器的角度看，数据的空间接近）。

公开(公告)号：US20100115204A1

公开(公告)日：2010-05-06

申请号：US12264682

申请日：2008-11-04

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Xiaoxia Wu ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Xiaoxia Wu ,  Lixin Zhang

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/123 ,  G06F2212/225 ,  G06F2212/271

摘要： In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.

摘要翻译： 在一个实施例中，高速缓冲存储器包括高速缓存阵列，其包括用于缓存高速缓存数据行的多个条目，其中多个条目分布在以第一存储器技术实现的第一区域和在第二存储器技术中实现的第二区域之间 。 高速缓冲存储器还包括高速缓存阵列的内容的高速缓存目录和控制高速缓冲存储器的操作的高速缓存控制器。

公开(公告)号：US20070283101A1

公开(公告)日：2007-12-06

申请号：US11422459

申请日：2006-06-06

申请人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

发明人： Wael R. El-Essawy ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.

摘要翻译： 一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。 该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。 该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求） 使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

公开(公告)号：US07281092B2

公开(公告)日：2007-10-09

申请号：US11143328

申请日：2005-06-02

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0817 ,  G06F12/0822

摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.

摘要翻译： 一种使用自适应机制管理缓存层次结构的系统和方法。 本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据 块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。 此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块 内存缓存被驱逐。

公开(公告)号：US08271729B2

公开(公告)日：2012-09-18

申请号：US12562242

申请日：2009-09-18

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。

公开(公告)号：US20110072214A1

公开(公告)日：2011-03-24

申请号：US12562242

申请日：2009-09-18

申请人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

发明人： Jian Li ,  Ramakrishnan Rajamony ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0848 ,  G06F2212/271 ,  Y02D10/13

摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

摘要翻译： 在缓存中提供了一种机制，用于提供读写感知高速缓存。 该机制将大型缓存分区分为常读区域和经常写区域。 该机制将读/写频率视为非均匀缓存架构替换策略。 经常写入的高速缓存行放置在更远的存储区之一中。 经常读取的高速缓存行被放置在其中一个较近的存储体中。 常读区域和经常写区域之间的大小比可以是静态的或动态的。 经常读区域和经常写区域之间的边界可能是不同的或模糊的。