摘要:
A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field. The unlocking device includes: a bottom housing; an operating unit; a latching unit; an elastic element; and a briquetting; wherein: the latching unit is movably engaged with the bottom housing; the elastic element is provided between the latching unit and the bottom housing, and the latching unit can be movable relative to the bottom housing under the elastic force of the elastic element; the operating unit is configured to be engaged with the bottom housing, when an external force from an operator is applied to the operating unit, the operating unit pivots around a pivot axis thereof with respect to the bottom housing to drive the latching unit so that the latching unit can be movable between a locked position and an unlocked position with respect to the bottom housing; and the briquetting is fixed on the bottom housing and engages with the operating unit, when the latching unit is located at the unlocked position, the briquetting restricts the pivot movement of the operating unit around the pivot axis with respect to the bottom housing.
摘要:
A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field. The unlocking device includes: a bottom housing; an operating unit; a latching unit; an elastic element; and a briquetting; wherein: the latching unit is movably engaged with the bottom housing; the elastic element is provided between the latching unit and the bottom housing, and the latching unit can be movable relative to the bottom housing under the elastic force of the elastic element; the operating unit is configured to be engaged with the bottom housing, when an external force from an operator is applied to the operating unit, the operating unit pivots around a pivot axis thereof with respect to the bottom housing to drive the latching unit so that the latching unit can be movable between a locked position and an unlocked position with respect to the bottom housing; and the briquetting is fixed on the bottom housing and engages with the operating unit, when the latching unit is located at the unlocked position, the briquetting restricts the pivot movement of the operating unit around the pivot axis with respect to the bottom housing.
摘要:
An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.
摘要:
An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.
摘要:
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
摘要:
A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.
摘要:
Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.
摘要:
The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.
摘要:
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
摘要:
Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.