Bail Type Unlocking Device for Opto-Electronic Module
    1.
    发明申请
    Bail Type Unlocking Device for Opto-Electronic Module 有权
    用于光电模块的保释型解锁装置

    公开(公告)号:US20090279831A1

    公开(公告)日:2009-11-12

    申请号:US12306174

    申请日:2006-11-07

    IPC分类号: G02B6/36 G02B6/00

    摘要: A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field. The unlocking device includes: a bottom housing; an operating unit; a latching unit; an elastic element; and a briquetting; wherein: the latching unit is movably engaged with the bottom housing; the elastic element is provided between the latching unit and the bottom housing, and the latching unit can be movable relative to the bottom housing under the elastic force of the elastic element; the operating unit is configured to be engaged with the bottom housing, when an external force from an operator is applied to the operating unit, the operating unit pivots around a pivot axis thereof with respect to the bottom housing to drive the latching unit so that the latching unit can be movable between a locked position and an unlocked position with respect to the bottom housing; and the briquetting is fixed on the bottom housing and engages with the operating unit, when the latching unit is located at the unlocked position, the briquetting restricts the pivot movement of the operating unit around the pivot axis with respect to the bottom housing.

    摘要翻译: 一种用于光电模块的保释型解锁装置,其涉及光通信领域中用于热插拔型光电模块的解锁装置。 解锁装置包括:底部壳体; 操作单元 锁定单元; 弹性元件 和一个压块; 其中:所述闩锁单元与所述底部壳体可移动地接合; 弹性元件设置在闩锁单元和底部壳体之间,并且闩锁单元可以在弹性元件的弹力下相对于底部壳体移动; 操作单元构造成与底部壳体接合,当来自操作者的外力施加到操作单元时,操作单元围绕其相对于底部壳体的枢转轴线枢转以驱动闩锁单元,使得 闩锁单元可以相对于底部壳体在锁定位置和解锁位置之间移动; 并且压块固定在底部壳体上并与操作单元接合,当闩锁单元位于解锁位置时,压块将操作单元围绕枢转轴线相对于底部壳体的枢转运动限制。

    Bail type unlocking device for opto-electronic module
    2.
    发明授权
    Bail type unlocking device for opto-electronic module 有权
    用于光电模块的保释型解锁装置

    公开(公告)号:US07883274B2

    公开(公告)日:2011-02-08

    申请号:US12306174

    申请日:2006-11-07

    IPC分类号: G02B6/36

    摘要: A bail type-unlocking device for an opto-electronic module, which pertains to an unlocking device for a hot pluggable type opto-electronic module in the optical communication field. The unlocking device includes: a bottom housing; an operating unit; a latching unit; an elastic element; and a briquetting; wherein: the latching unit is movably engaged with the bottom housing; the elastic element is provided between the latching unit and the bottom housing, and the latching unit can be movable relative to the bottom housing under the elastic force of the elastic element; the operating unit is configured to be engaged with the bottom housing, when an external force from an operator is applied to the operating unit, the operating unit pivots around a pivot axis thereof with respect to the bottom housing to drive the latching unit so that the latching unit can be movable between a locked position and an unlocked position with respect to the bottom housing; and the briquetting is fixed on the bottom housing and engages with the operating unit, when the latching unit is located at the unlocked position, the briquetting restricts the pivot movement of the operating unit around the pivot axis with respect to the bottom housing.

    摘要翻译: 一种用于光电模块的保释型解锁装置,其涉及光通信领域中用于热插拔型光电模块的解锁装置。 解锁装置包括:底部壳体; 操作单元 锁定单元; 弹性元件 和一个压块; 其中:所述闩锁单元与所述底部壳体可移动地接合; 弹性元件设置在闩锁单元和底部壳体之间,并且闩锁单元可以在弹性元件的弹力下相对于底部壳体移动; 操作单元构造成与底部壳体接合,当来自操作者的外力施加到操作单元时,操作单元围绕其相对于底部壳体的枢转轴线枢转以驱动闩锁单元,使得 闩锁单元可以相对于底部壳体在锁定位置和解锁位置之间移动; 并且压块固定在底部壳体上并与操作单元接合,当闩锁单元位于解锁位置时,压块将操作单元围绕枢转轴线相对于底部壳体的枢转运动限制。

    Bail type unlocking and resetting device for hot pluggable opto-electronic module
    3.
    发明授权
    Bail type unlocking and resetting device for hot pluggable opto-electronic module 有权
    用于热插拔光电模块的保释型解锁和复位装置

    公开(公告)号:US07712969B2

    公开(公告)日:2010-05-11

    申请号:US12438258

    申请日:2006-11-03

    IPC分类号: G02B6/36

    摘要: An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.

    摘要翻译: 一种用于光电模块的解锁和复位装置包括具有盲孔和水平滑槽的壳体,以及第一和第二安装部分; 弹性片 如地狱; 第一泉 适于插入所述盲孔中的插入块; 适于插入并设置在所述水平滑槽中的制动构件; 第二泉 适于安装在第一和第二安装部分上的第一和第二按压块; 和具有凸轮部分的保释。 解锁和复位装置的单臂吊环可以自动返回起始位置,无需手动重新定位。

    Bail Type Unlocking and Resetting Device for Hot Pluggable Opto-electronic Module
    4.
    发明申请
    Bail Type Unlocking and Resetting Device for Hot Pluggable Opto-electronic Module 有权
    用于热插拔光电模块的拨号类型解锁和复位装置

    公开(公告)号:US20090321301A1

    公开(公告)日:2009-12-31

    申请号:US12438258

    申请日:2006-11-03

    IPC分类号: B65D85/00

    摘要: An unlocking and resetting device for an opto-electronic module comprises a casing having a blind hole and a horizontal slide slot, and first and second mounting parts; an elastic piece; a shell; first springs; an insert block adapted to be inserted into the blind hole; a brake member adapted to be inserted and disposed in the horizontal slide slot; second springs; first and second pressing blocks adapted to be mounted onto first and second mounting parts; and a bail having a cam portion. The single-arm bail of the unlocking and resetting device can return the start position automatically without manual repositions.

    摘要翻译: 一种用于光电模块的解锁和复位装置包括具有盲孔和水平滑槽的壳体,以及第一和第二安装部分; 弹性片 如地狱; 第一泉 适于插入所述盲孔中的插入块; 适于插入并设置在所述水平滑槽中的制动构件; 第二泉 适于安装在第一和第二安装部分上的第一和第二按压块; 和具有凸轮部分的保释。 解锁和复位装置的单臂吊环可以自动返回起始位置,无需手动重新定位。

    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
    5.
    发明授权
    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations 有权
    通过考虑系统和随机的模内工艺变化来预测IC制造产量

    公开(公告)号:US08000826B2

    公开(公告)日:2011-08-16

    申请号:US11339184

    申请日:2006-01-24

    摘要: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

    摘要翻译: 本发明的一个实施例提供了一种系统,其预测半导体晶片内的管芯的制造成品率。 在操作期间,系统首先接收模具的物理布局。 接下来,系统将模具分割成瓦片阵列。 然后,该系统计算质量指示值的系统变化,以基于模具的物理布局描述整个瓦片阵列上的过程参数。 接下来,系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。 最后,系统基于系统变化和随机变量得到了模具的制造成品率。

    Simulating topography of a conductive material in a semiconductor wafer
    6.
    发明授权
    Simulating topography of a conductive material in a semiconductor wafer 有权
    模拟半导体晶片中导电材料的形貌

    公开(公告)号:US07289933B2

    公开(公告)日:2007-10-30

    申请号:US11267776

    申请日:2005-11-04

    IPC分类号: G01B11/24 H01L21/31

    CPC分类号: G06F17/5009 G06F2217/74

    摘要: A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.

    摘要翻译: 半导体晶片中的导电材料的尺寸由计算机确定,该计算机将与导电材料的侧壁的有效表面积成比例的导电材料的体积相当(a),并且(b)导电材料的体积 基于导电材料中的导电沟槽(如果存在)的宽度与绝缘沟槽的宽度不同的预定量的几何形状。 在一些实施例中,计算机计算有效表面积作为沟槽深度和布局参数的乘积,其中的一个或两个可以从包含几个拓扑图的测试晶片部分或全部经验地确定。 如果满足预定条件,计算机将计算假设一个地形的尺寸并验证该假设。 如果不符合条件,计算机会重新计算尺寸,假设其他地形。

    ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY
    7.
    发明申请
    ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY 有权
    路由分析与双模式图

    公开(公告)号:US20120216157A1

    公开(公告)日:2012-08-23

    申请号:US13400411

    申请日:2012-02-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

    摘要翻译: 描述了双模式光刻的图形分析。 布局形状分解为矩形,并为每个矩形提供一个顶点。 确定双重图案间距冲突,并将其显示为图形分析的边。 奇数周期用于识别双重图案光刻违规。 可以通过在布局中包含针迹的顶点之间添加边缘来完成循环。 触摸形状之间的边缘不计入循环中的奇数。 通过增加空间或重新路由来增加修复。 布局的一部分可以递增地改变,并且执行图分析的本地更新。 通过施工布局进行校正是通过避免某些奇怪的周期倾向布局布线来实现的。

    Dummy Filling Technique For Improved Planarization Of Chip Surface Topography
    8.
    发明申请
    Dummy Filling Technique For Improved Planarization Of Chip Surface Topography 有权
    用于改进芯片表面形貌平面化的虚拟填充技术

    公开(公告)号:US20070245284A1

    公开(公告)日:2007-10-18

    申请号:US11379043

    申请日:2006-04-17

    IPC分类号: G06F17/50 G06F19/00

    摘要: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

    摘要翻译: 在虚拟填充期间使用平滑的后ECP拓扑(而不是最终的芯片地形)作为目标,可以在保持解决方案质量的同时,为铜提供基于计算的基于模型的虚拟填充解决方案。 每个瓷砖的布局可分为瓷砖和案例。 示例性情况可以包括适形填充,过填充,超填充或超/过填充(如果ECP模型不能区分超填充和过填充情况)。 可以将一个或多个不需要的瓦片情况转换为期望的瓦片情况。 然后,可以最小化瓦片之间的高度差。 可以在布局中插入虚拟功能以执行转换,并最小化拼贴之间的高度差异。 可以执行使用ECP考虑最小化瓷砖之间的CMP有效密度差,以进一步改善平面化。

    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
    9.
    发明申请
    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations 有权
    通过考虑系统和随机的模内工艺变化来预测IC制造产量

    公开(公告)号:US20070174797A1

    公开(公告)日:2007-07-26

    申请号:US11339184

    申请日:2006-01-24

    IPC分类号: G06F17/50

    摘要: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

    摘要翻译: 本发明的一个实施例提供了一种系统,其预测半导体晶片内的管芯的制造成品率。 在操作期间,系统首先接收模具的物理布局。 接下来,系统将模具分割成瓦片阵列。 然后,该系统计算质量指示值的系统变化,以基于模具的物理布局描述整个瓦片阵列上的过程参数。 接下来,系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。 最后,系统基于系统变化和随机变量得到了模具的制造成品率。

    Routing analysis with double pattern lithography
    10.
    发明授权
    Routing analysis with double pattern lithography 有权
    双模光刻的路由分析

    公开(公告)号:US08856697B2

    公开(公告)日:2014-10-07

    申请号:US13400411

    申请日:2012-02-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

    摘要翻译: 描述了双模式光刻的图形分析。 布局形状分解为矩形,并为每个矩形提供一个顶点。 确定双重图案间距冲突,并将其显示为图形分析的边。 奇数周期用于识别双重图案光刻违规。 可以通过在布局中包含针迹的顶点之间添加边缘来完成循环。 触摸形状之间的边缘不计入循环中的奇数。 通过增加空间或重新路由来增加修复。 布局的一部分可以递增地改变,并且执行图分析的本地更新。 通过施工布局进行校正是通过避免某些奇怪的周期倾向布局布线来实现的。