公开(公告)号：US07509622B2

公开(公告)日：2009-03-24

申请号：US11379043

申请日：2006-04-17

Applicant: Subarnarekha Sinha ,  Jianfeng Luo ,  Charles C. Chiang

Inventor： Subarnarekha Sinha ,  Jianfeng Luo ,  Charles C. Chiang

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  H01L21/3212 ,  Y02P90/265

Abstract: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the “case” of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

Abstract translation: 在虚拟填充期间使用平滑的后ECP拓扑（而不是最终的芯片地形）作为目标，可以在保持解决方案质量的同时，为铜提供基于计算的基于模型的虚拟填充解决方案。 布局可以分为瓦片和标识的每个瓦片的“案例”。 示例性情况可以包括适形填充，过填充，超填充或超/过填充（如果ECP模型不能区分超填充和过填充情况）。 可以将一个或多个不需要的瓦片情况转换为期望的瓦片情况。 然后，可以最小化瓦片之间的高度差。 可以在布局中插入虚拟功能以执行转换，并最小化拼贴之间的高度差异。 可以执行使用ECP考虑最小化瓷砖之间的CMP有效密度差，以进一步改善平面化。

公开(公告)号：US20070192751A1

公开(公告)日：2007-08-16

申请号：US11725007

申请日：2007-03-16

Applicant: Subarnarekha Sinha ,  Qing Su ,  Charles Chiang

Inventor： Subarnarekha Sinha ,  Qing Su ,  Charles Chiang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.

Abstract translation: 本发明的一个实施方案提供了减少随机产率损失的系统。 在操作过程中，系统可以接收设计布局。 系统还可以接收与金属区域和空区域中的颗粒密度相关联的加权因子。 接下来，系统可以确定一组线段的局部临界面积比和优化电位。 然后，系统可以选择一个线段，并将其局部临界面积比与全局临界面积比进行比较。 接下来，系统可以使用比较结果来确定布局优化。 然后，系统可以将布局优化应用于线段以获得改进的布局。

公开(公告)号：US20060199083A1

公开(公告)日：2006-09-07

申请号：US11127694

申请日：2005-05-11

Applicant: Subarnarekha Sinha ,  Charles Chiang

Inventor： Subarnarekha Sinha ,  Charles Chiang

IPC: G03C5/00 ,  G03F9/00 ,  G06F17/50 ,  G03F1/00

CPC classification number: G03F1/30

Abstract: One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout such that the PSM-layout is phase-assignable if and only if the phase-conflict graph is bipartite. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. The system can also be used to correct a given set of phase conflicts in a PSM-layout. The system identifies a set of lines in the layout, such that adding space along the set of lines will result in a phase-assignable PSM-layout. A substantially minimal set of lines can be determined by solving an equivalent minimum-weight set covering problem.

Abstract translation: 本发明的一个实施例提供了一种系统，其识别PSM布局中的基本上最小的相位冲突集合，其在被校正时呈现布局相位可分配。 在操作期间，系统从PSM布局构建相冲突图，使得当且仅当相冲突图是二分的时候，PSM布局是可相位分配的。 接下来，系统从相冲突图中移除第一组边，使图形平面，然后移除第二组边，使图形成二分。 然后，系统添加第一组边缘的零个或多个边缘，并且基于第一组边缘和第二组边缘中的剩余边缘来确定PSM布局中的一组相位冲突。 该系统还可用于纠正PSM布局中给定的一组相位冲突。 系统识别布局中的一组线，使得沿着该组线添加空间将导致相位可分配的PSM布局。 可以通过求解等效的最小权重集合覆盖问题来确定基本上最小的一组线。

公开(公告)号：US20090150850A1

公开(公告)日：2009-06-11

申请号：US12388454

申请日：2009-02-18

Applicant: Subarnarekha Sinha ,  Charles C. Chiang

Inventor： Subarnarekha Sinha ,  Charles C. Chiang

IPC: G06F17/50

CPC classification number: G03F1/30

Abstract: One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. Next, the system identifies a set of lines in the layout, such that adding space along the set of lines results in a phase-assignable PSM-layout.

Abstract translation: 本发明的一个实施例提供了一种系统，其识别PSM布局中的基本上最小的相位冲突集合，其在被校正时呈现布局相位可分配。 在操作期间，系统从PSM布局构建相冲突图。 接下来，系统从相冲突图中移除第一组边，使图形平面，然后移除第二组边，使图形成二分。 然后，系统添加第一组边缘的零个或多个边缘，并且基于第一组边缘和第二组边缘中的剩余边缘来确定PSM布局中的一组相位冲突。 接下来，系统识别布局中的一组线，使得沿着该组线添加空间导致相位可分配的PSM布局。

公开(公告)号：US20090138835A1

公开(公告)日：2009-05-28

申请号：US12362721

申请日：2009-01-30

Applicant: Subarnarekha Sinha ,  Hailong Yao ,  Charles C. Chiang

Inventor： Subarnarekha Sinha ,  Hailong Yao ,  Charles C. Chiang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.

Abstract translation: 范围模式通过对布局块和范围模式进行切片来匹配IC布局块，然后将布局片段的宽度序列与模式片段的宽度范围序列进行比较，如果任何布局片段的宽度下降 在对应的图案切片的宽度范围之外，则布局块与范围图案不匹配。 如果比较成功，则在每个布局切片中的布局片段的长度序列和相应图案片段中的片段片段的长度范围的序列之间进行进一步的比较。 如果任何布局片段的长度落在相应图案片段的长度范围之外，则该块与范围模式不匹配。 如果所有长度在其各自的范围内，则块在匹配模式时，尽管在一些实施例中检查了附加的约束。

公开(公告)号：US20080148196A1

公开(公告)日：2008-06-19

申请号：US12032313

申请日：2008-02-15

Applicant: Qing Su ,  Subarnarekha Sinha ,  Charles C. Chiang

Inventor： Qing Su ,  Subarnarekha Sinha ,  Charles C. Chiang

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract translation: 用于近似布局或布局区域的平均临界区域的方法和装置，涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值，每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸，并且对于特定缺陷类型，贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

公开(公告)号：US07346865B2

公开(公告)日：2008-03-18

申请号：US10978946

申请日：2004-11-01

Applicant: Qing Su ,  Subarnarekha Sinha ,  Charles C. Chiang

Inventor： Qing Su ,  Subarnarekha Sinha ,  Charles C. Chiang

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract translation: 用于近似布局或布局区域的平均临界区域的方法和装置，涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值，每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸，并且对于特定缺陷类型，贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

公开(公告)号：US20070245284A1

公开(公告)日：2007-10-18

申请号：US11379043

申请日：2006-04-17

Applicant: Subarnarekha Sinha ,  Jianfeng Luo ,  Charles Chiang

Inventor： Subarnarekha Sinha ,  Jianfeng Luo ,  Charles Chiang

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  H01L21/3212 ,  Y02P90/265

Abstract: The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

Abstract translation: 在虚拟填充期间使用平滑的后ECP拓扑（而不是最终的芯片地形）作为目标，可以在保持解决方案质量的同时，为铜提供基于计算的基于模型的虚拟填充解决方案。 每个瓷砖的布局可分为瓷砖和案例。 示例性情况可以包括适形填充，过填充，超填充或超/过填充（如果ECP模型不能区分超填充和过填充情况）。 可以将一个或多个不需要的瓦片情况转换为期望的瓦片情况。 然后，可以最小化瓦片之间的高度差。 可以在布局中插入虚拟功能以执行转换，并最小化拼贴之间的高度差异。 可以执行使用ECP考虑最小化瓷砖之间的CMP有效密度差，以进一步改善平面化。

公开(公告)号：US20070174797A1

公开(公告)日：2007-07-26

申请号：US11339184

申请日：2006-01-24

Applicant: Jianfeng Luo ,  Subarnarekha Sinha ,  Qing Su ,  Charles Chiang

Inventor： Jianfeng Luo ,  Subarnarekha Sinha ,  Qing Su ,  Charles Chiang

IPC: G06F17/50

CPC classification number: G05B19/41875 ,  G05B2219/32204 ,  G05B2219/35142 ,  G05B2219/45031 ,  Y02P90/22

Abstract: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

Abstract translation: 本发明的一个实施例提供了一种系统，其预测半导体晶片内的管芯的制造成品率。 在操作期间，系统首先接收模具的物理布局。 接下来，系统将模具分割成瓦片阵列。 然后，该系统计算质量指示值的系统变化，以基于模具的物理布局描述整个瓦片阵列上的过程参数。 接下来，系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。 最后，系统基于系统变化和随机变量得到了模具的制造成品率。

公开(公告)号：US08566754B2

公开(公告)日：2013-10-22

申请号：US12275887

申请日：2008-11-21

Applicant: Kent Y. Kwang ,  Daniel Zhang ,  Zongwu Tang ,  Subarnarekha Sinha

Inventor： Kent Y. Kwang ,  Daniel Zhang ,  Zongwu Tang ,  Subarnarekha Sinha

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.

Abstract translation: 本发明的一个实施例提供一种自动处理制造热点信息的系统。 在操作期间，系统接收与布局中的制造热点相关联的图案剪辑，其中图案剪辑包括靠近制造热点位置的一组多边形。 接下来，系统确定模式剪辑是否匹配已知的制造热点配置。 如果图案剪辑与已知的制造热点配置不匹配，则系统然后对图案剪辑执行扰动处理，以确定一组校正建议以消除制造热点。 通过执行扰动过程，系统另外确定对该组多边形的扰动范围，其中扰动图案片不消除制造热点。 随后，系统将修正建议的集合和扰动范围存储到制造热点数据库中。