公开(公告)号：US06277723B1

公开(公告)日：2001-08-21

申请号：US09418030

申请日：1999-10-14

申请人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

IPC分类号： H01L2144

CPC分类号： H01L21/28123

摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

摘要翻译： 公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。 保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。 分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。 浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

公开(公告)号：US06207532B1

公开(公告)日：2001-03-27

申请号：US09408494

申请日：1999-09-30

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile. A layer of TEOS is deposited and polished leaving the trench filled with TEOS and at the same time removing the nitride from the surface of the pad oxide. N-well and P-well implants are performed after which N+ and P+ implants are performed around the periphery of the STI trench.

摘要翻译： 提供了一种创建浅沟槽隔离区域的新方法。 在衬底的表面上沉积一层衬垫氧化物; 在衬垫氧化物层上沉积一层氮化物。 衬垫氧化物和氮化物的层被图案化并蚀刻在要形成STI的区域上，在硅区域中蚀刻用于STI区域的沟槽。 用作缓冲间隔氧化物的TEOS层被沉积在氮化层的表面上，从而包括所产生的沟槽的内部。 蚀刻TEOS层从氮化物的表面和沟槽的底部去除TEOS，但是沿着沟槽的侧壁留下一层TEOS就位。 接下来蚀刻沟槽的底部，然后从沟槽的侧壁去除TEOS间隔物缓冲液。 沟槽的侧壁现在具有非线性轮廓。 沉积和抛光一层TEOS，留下填充有TEOS的沟槽，同时从衬垫氧化物的表面去除氮化物。 进行N阱和P阱注入，之后在STI沟槽周围进行N +和P +植入。

公开(公告)号：US06242314B1

公开(公告)日：2001-06-05

申请号：US09161407

申请日：1998-09-28

申请人： Shui-Hung Chen ,  Chrong Jung Lin ,  Jiaw-Ren Shih

发明人： Shui-Hung Chen ,  Chrong Jung Lin ,  Jiaw-Ren Shih

IPC分类号： H01L2120

CPC分类号： H01L28/20

摘要： A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors. The first and second poly-load resistors can have different implant dose to get the desired cut off temperatures.

摘要翻译： 通过将P型和N型离子共注入到多重负载电阻器中来制造片上温度控制器的方法。 可以选择N型和P型植入剂量以产生所需的截止温度。 首先，在第一绝缘层20上形成多晶硅层30.多晶硅层30被构图以形成第一多重负载电阻器30A和第二多重负载电阻器30B。 第一和第二多负载电阻器连接到温度传感器电路12.P型和n型杂质离子都注入到多晶硅层30中。绝缘电介质层40形成在多晶硅层30上，并且 第一绝缘层20.多晶硅层退火。 接触开口44通过暴露多晶硅层30的部分的ILD电介质层40形成。触头50连接到多晶硅层30，从而形成第一和第二多负载电阻器，其使用温度片上传感器。 第一和第二多负载电阻器可以具有不同的植入剂量以获得期望的截止温度。

公开(公告)号：US20050176195A1

公开(公告)日：2005-08-11

申请号：US11072014

申请日：2005-03-04

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

公开(公告)号：US06614078B2

公开(公告)日：2003-09-02

申请号：US10147272

申请日：2002-05-16

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921

摘要： CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

公开(公告)号：US06614693B1

公开(公告)日：2003-09-02

申请号：US10100752

申请日：2002-03-19

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/16

摘要： A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

摘要翻译： 从闪存EEPROM擦除数据的组合擦除方法消除了在快速EEPROM的隧道氧化物中捕获的电荷，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的第一实施例方法是通过负栅极擦除开始，以从浮置栅极去除电荷，随后进行源擦除以进一步从浮置栅极去除电荷，最后再进行通道擦除以去除电荷。 第二实施例开始于负栅极擦除，其具有电压的增量步进以从浮置栅极去除电荷。 之后是源擦除来去除EEPROM单元的隧道氧化物。 第三实施例开始于具有逐渐增加的步进电压以从浮动栅极去除电荷的源擦除。 之后是通道擦除以去除EEPROM单元的隧穿氧化物。

公开(公告)号：US06541824B2

公开(公告)日：2003-04-01

申请号：US09957275

申请日：2001-09-21

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0277 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.

公开(公告)号：US06362035B1

公开(公告)日：2002-03-26

申请号：US09498741

申请日：2000-02-07

申请人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

IPC分类号： H01L2144

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  Y10S438/919

摘要： A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

摘要翻译： 描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。 通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。 随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。 在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。 该方法在利用浅沟槽隔离的工艺中示出并且特别有效。

公开(公告)号：US06190954B1

公开(公告)日：2001-02-20

申请号：US09229381

申请日：1999-01-11

申请人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

发明人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

IPC分类号： H01L218238

CPC分类号： H01L21/823892 ,  H01L27/0921

摘要： A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

摘要翻译： 公开了一种通过增加存在于CMOS结构中的寄生npn和pnp晶体管的跳转电压VBO或触发点来提供更稳健的闭锁免疫CMOS晶体管的方法。 这些目标已经通过在双井CMOS结构的n阱和p阱两者中添加阻挡层来实现，从而分别增加了寄生npn和pnp晶体管的电子和空穴的能隙。

公开(公告)号：US06323523B1

公开(公告)日：2001-11-27

申请号：US09494682

申请日：2000-01-31

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.

摘要翻译： 公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。 在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区， 上拉晶体管耦合到电源。 下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。 包括p +保护的下拉晶体管的所有源极区域接地。 所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。