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1.发明授权Message signaled interrupt extended (MSI-X) auto clear and failsafe lock 有权消息信号中断扩展（MSI-X）自动清除和故障安全锁定公开(公告)号：US07565471B2
公开(公告)日：2009-07-21
申请号：US11228862
申请日：2005-09-16
CPC分类号： G06F13/24 , Y10S707/99953 , Y10S707/99955
摘要： A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no interrupts are lost in the process. In particular, an auto clear function is employed to eliminate the need for drivers in the host to send writes over the PCI-based bus to deassert and assert attention enable register bits and clear down attention register bits, and a fail safe mechanism is utilized to prevent lost interrupts.
摘要翻译： 公开了一种用于通过实现用于中断条件的有效递送和清除机制来提高MSI和MSI-X规范以提高驱动器和硬件/固件接口之间的性能同时确保在该过程中不会中断丢失的方法和装置。 特别地，采用自动清除功能来消除对主机中的驱动程序的需求，以通过基于PCI的总线发送写入，以断言并声明注意使能寄存器位并清除注意事件寄存器位，并且使用故障安全机制 防止丢失中断。
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公开(公告)号：US07765336B2
公开(公告)日：2010-07-27
申请号：US11811716
申请日：2007-06-11
IPC分类号： G06F3/00
CPC分类号： H04L49/9042 , H04L49/90
摘要： A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.
摘要翻译： 公开了一种基于硬件的卸载引擎，用于将受保护的数据映射到帧中。 对于写操作，HBA确定要从这些地址读取的数据的主机地址和大小。 HBA还确定要写入的数据的帧大小和保护方案。 帧发送引擎读取主机数据描述符列表中的每个主机描述符，以确定要读取的数据的位置和字节数。 DMA引擎读取保护信息/划痕区域以确定用于填充每个帧和保护方案的确切数据大小，并检索一个或多个空闲帧缓冲区。 检查字节与数据一起插入并存储在空闲帧缓冲区中。 在每个帧被填满之后，帧发送引擎也生成并存储该帧的报头信息，然后组合报头，数据和检查字节以便在网络上传输。
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公开(公告)号：US20080307122A1
公开(公告)日：2008-12-11
申请号：US11811716
申请日：2007-06-11
IPC分类号： G06F13/28
CPC分类号： H04L49/9042 , H04L49/90
摘要： A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.
摘要翻译： 公开了一种基于硬件的卸载引擎，用于将受保护的数据映射到帧中。 对于写操作，HBA确定要从这些地址读取的数据的主机地址和大小。 HBA还确定要写入的数据的帧大小和保护方案。 帧发送引擎读取主机数据描述符列表中的每个主机描述符，以确定要读取的数据的位置和字节数。 DMA引擎读取保护信息/划痕区域以确定用于填充每个帧和保护方案的确切数据大小，并检索一个或多个空闲帧缓冲区。 检查字节与数据一起插入并存储在空闲帧缓冲区中。 在每个帧被填满之后，帧发送引擎也生成并存储该帧的报头信息，然后组合报头，数据和检查字节以便在网络上传输。
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公开(公告)号：US07062615B2
公开(公告)日：2006-06-13
申请号：US10651890
申请日：2003-08-29
IPC分类号： G06F12/00
CPC分类号： G06F9/526
摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.
摘要翻译： 一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。 在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性 和时机。
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5.发明授权System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur 失效在没有处理器干预的情况下直接从主机访问主机的系统和方法，其中不会发生在主机启动期间自动访问存储器公开(公告)号：US07149823B2
公开(公告)日：2006-12-12
申请号：US10651887
申请日：2003-08-29
CPC分类号： G06F13/385 , G06F13/28
摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.
摘要翻译： 一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。 在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。 主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。 通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。
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