公开(公告)号：US06838900B2

公开(公告)日：2005-01-04

申请号：US09967746

申请日：2001-09-28

Applicant: Jin-Cheng Huang ,  Ching Fu Chuang

Inventor： Jin-Cheng Huang ,  Ching Fu Chuang

IPC: H04L25/02 ,  H05K1/02 ,  H03K17/16

CPC classification number: H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0246 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract translation: 用于在不同集成电路之间应用数据传输的总线架构。 总线架构包括至少一条与IC的I / O引脚连接的传输线，用于发送数据。 在传输线的中点处，存在电阻值优选等于传输线的特性阻抗的中间电阻。 此外，IC内部有上拉电阻，其具有耦合到I / O引脚的第一端和耦合到电压源的第二端。 每个上拉电阻具有比传输线的特性阻抗高的电阻值，例如特性阻抗的2或3倍，用于抑制上升沿回波。