公开(公告)号：US06838900B2

公开(公告)日：2005-01-04

申请号：US09967746

申请日：2001-09-28

Applicant: Jin-Cheng Huang ,  Ching Fu Chuang

Inventor： Jin-Cheng Huang ,  Ching Fu Chuang

IPC: H04L25/02 ,  H05K1/02 ,  H03K17/16

CPC classification number: H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0246 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract translation: 用于在不同集成电路之间应用数据传输的总线架构。 总线架构包括至少一条与IC的I / O引脚连接的传输线，用于发送数据。 在传输线的中点处，存在电阻值优选等于传输线的特性阻抗的中间电阻。 此外，IC内部有上拉电阻，其具有耦合到I / O引脚的第一端和耦合到电压源的第二端。 每个上拉电阻具有比传输线的特性阻抗高的电阻值，例如特性阻抗的2或3倍，用于抑制上升沿回波。

公开(公告)号：US6133757A

公开(公告)日：2000-10-17

申请号：US156032

申请日：1998-09-17

Applicant: Jin-Cheng Huang ,  Yuantsang Liaw

Inventor： Jin-Cheng Huang ,  Yuantsang Liaw

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC classification number: H03K17/164 ,  H03K19/00361

Abstract: A high-speed and low-noise output buffer with a slew control function in coordination with a GTL+ signal specification according to the invention. In the output buffer, general and speed driving elements concurrently drives a last output element. As an input signal is changed from a first logic level to a second logic level, the general and speed driving elements simultaneously start functioning. First, the speed driving element pulls down the control voltage of the output element to a potential having a potential difference from an expected final potential. Then, the general driving element pulls down the control voltage to close to the expected final potential. The output potential of the output element changes more quickly at the beginning. When close to the expected final potential, the variation of the output potential slows down. Since, the delay time of the output buffer is reduced without causing an over large ring back on the output signal, the output buffer with high-speed and low-noise can be obtained.

Abstract translation: 具有与根据本发明的GTL +信号规范协调的转换控制功能的高速和低噪声输出缓冲器。 在输出缓冲器中，通用和速度驱动元件同时驱动最后一个输出元件。 当输入信号从第一逻辑电平变为第二逻辑电平时，通用和速度驱动元件同时起动。 首先，速度驱动元件将输出元件的控制电压下降到具有与期望的最终电位的电位差的电位。 然后，通用驱动元件将控制电压拉低以接近预期的最终电位。 输出元件的输出电位在开始时变化较快。 当接近预期的最终电位时，输出电位的变化将减慢。 由于输出缓冲器的延迟时间减小，而不会在输出信号上产生过大的环路，所以可以获得具有高速和低噪声的输出缓冲器。

公开(公告)号：US06744646B2

公开(公告)日：2004-06-01

申请号：US09975322

申请日：2001-10-12

Applicant: Jin-Cheng Huang ,  Yen-Mou Huang

Inventor： Jin-Cheng Huang ,  Yen-Mou Huang

IPC: H02M318

CPC classification number: G05F3/247

Abstract: A device and method for converting a low voltage signal into a high voltage signal are provided, which can be implemented by using a low voltage CMOS manufacturing process to convert a low voltage signal of 0V to 1.5V into a high voltage signal of 2.5V to 1.25V. According to one preferred embodiment, PMOS transistors are employed to perform voltage level conversion and supply voltages of 1.25V and 2.5V are supplied to the PMOS transistors. During the conversion, no current path exists between the supply voltages thus effectively reducing static power consumption. In addition, the low level of the high voltage signal is outputted through the drain and source of the transistor so that the low level of the high voltage signal can be accurately defined and not affected by manufacturing parameters.

Abstract translation: 提供了一种用于将低电压信号转换成高电压信号的装置和方法，其可以通过使用低电压CMOS制造工艺来实现，以将0V至1.5V的低电压信号转换成2.5V的高电压信号， 1.25V。 根据一个优选实施例，使用PMOS晶体管来执行电压电平转换，并且向PMOS晶体管提供1.25V和2.5V的电源电压。 在转换期间，电源电压之间不存在电流路径，从而有效降低了静态功耗。 此外，高电平信号的低电平通过晶体管的漏极和源极输出，使得高电平信号的低电平可以被精确地定义并且不受制造参数的影响。

公开(公告)号：US06590827B2

公开(公告)日：2003-07-08

申请号：US09955781

申请日：2001-09-19

Applicant: Nai-Shung Chang ,  Jin-Cheng Huang

Inventor： Nai-Shung Chang ,  Jin-Cheng Huang

IPC: G11C800

CPC classification number: G11C7/225 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/151

Abstract: A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.