公开(公告)号：US20090137117A1

公开(公告)日：2009-05-28

申请号：US12271220

申请日：2008-11-14

申请人： Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

发明人： Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76862

摘要： Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H2 remote plasma treating the W/WN barrier layer, forming a W-plug on the H2 remote plasma treated W/WN barrier layer to fill the contact hole, and chemical mechanical polishing (CMP) the W-plug and then the W/WN barrier layer in order to expose the interlayer insulating layer.

摘要翻译： 提供了形成半导体器件的接触插塞的方法。 形成半导体器件的接触插塞的方法可以包括在其上形成下部结构的半导体衬底上形成层间绝缘层，在层间绝缘层中形成接触孔，暴露下部结构的接触孔，并形成 W层，然后形成WN层，以在接触孔中形成W / WN阻挡层。 方法可以包括H2远程等离子体处理W / WN阻挡层，在H2远程等离子体处理的W / WN阻挡层上形成W-塞以填充接触孔，以及化学机械抛光（CMP）W-塞，然后 W / WN阻挡层，以露出层间绝缘层。

公开(公告)号：US08288275B2

公开(公告)日：2012-10-16

申请号：US12271220

申请日：2008-11-14

申请人： Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

发明人： Jin-ho Park ,  Gil-heyun Choi ,  Sang-woo Lee ,  Jun-ho Park ,  Ho-ki Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76862

摘要： Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include H2 remote plasma treating the W/WN barrier layer, forming a W-plug on the H2 remote plasma treated W/WN barrier layer to fill the contact hole, and chemical mechanical polishing (CMP) the W-plug and then the W/WN barrier layer in order to expose the interlayer insulating layer.

摘要翻译： 提供了形成半导体器件的接触插塞的方法。 形成半导体器件的接触插塞的方法可以包括在其上形成下部结构的半导体衬底上形成层间绝缘层，在层间绝缘层中形成接触孔，暴露下部结构的接触孔，并形成 W层，然后形成WN层，以在接触孔中形成W / WN阻挡层。 方法可以包括H2远程等离子体处理W / WN阻挡层，在H2远程等离子体处理的W / WN阻挡层上形成W-塞以填充接触孔，以及化学机械抛光（CMP）W-塞，然后 W / WN阻挡层，以露出层间绝缘层。

公开(公告)号：US20120216954A1

公开(公告)日：2012-08-30

申请号：US13459275

申请日：2012-04-30

申请人： Jin-ho PARK ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

发明人： Jin-ho PARK ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

IPC分类号： H01L21/306 ,  C23C16/455

CPC分类号： C23C16/45519 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4557

摘要： An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.

摘要翻译： 用于制造半导体器件的装置和方法可以通过减少微粒的产生和减少清洗次数来提高操作效率来增加半导体器件的可靠性。 该装置可以包括具有盖板的室，用于将半导体衬底牢固地放置在室内的基座，位于盖板上的喷淋头以将反应气体供应到室中，以及连接到盖板以提供加热帘幕的帘式气体管线 淋浴头之间的气体。

公开(公告)号：US20080214012A1

公开(公告)日：2008-09-04

申请号：US12007517

申请日：2008-01-11

申请人： Jin-ho Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

发明人： Jin-ho Park ,  Seong-hwee Cheong ,  Gil-heyun Choi ,  Sang-woo Lee ,  Ho-ki Lee

IPC分类号： H01L21/302 ,  C23C16/455

CPC分类号： C23C16/45519 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4557

摘要： An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.

摘要翻译： 用于制造半导体器件的装置和方法可以通过减少微粒的产生和减少清洗次数来提高操作效率来增加半导体器件的可靠性。 该装置可以包括具有盖板的室，用于将半导体衬底牢固地放置在室内的基座，位于盖板上的喷淋头以将反应气体供应到室中，以及连接到盖板以提供加热帘幕的帘式气体管线 淋浴头之间的气体。

公开(公告)号：US20100112772A1

公开(公告)日：2010-05-06

申请号：US12460945

申请日：2009-07-27

申请人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

发明人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

摘要翻译： 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

公开(公告)号：US20100105198A1

公开(公告)日：2010-04-29

申请号：US12458767

申请日：2009-07-22

申请人： Sang-woo Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

发明人： Sang-woo Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11568

摘要： A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.

摘要翻译： 形成半导体器件的栅电极的方法包括在衬底的外围电路区域中形成第一多晶硅层，在第一多晶硅层上形成阻挡层，阻挡层提供欧姆接触，形成包括 隧道绝缘层，电荷存储层和隔离绝缘层，在所述衬底的存储单元区域中，在所述阻挡层和所述阻挡绝缘层上形成第二多晶硅层，并且将所述第二多晶硅层硅化并形成硅化物栅极 电极。

公开(公告)号：US07998810B2

公开(公告)日：2011-08-16

申请号：US12424922

申请日：2009-04-16

申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

摘要翻译： 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

公开(公告)号：US07968410B2

公开(公告)日：2011-06-28

申请号：US12460945

申请日：2009-07-27

申请人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

发明人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

摘要翻译： 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。

公开(公告)号：US07521357B2

公开(公告)日：2009-04-21

申请号：US11063936

申请日：2005-02-23

申请人： Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

发明人： Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76841 ,  H01L21/76856 ,  H01L21/76877

摘要： A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer inside the contact hole. A conductive layer can be formed on the etch stop layer outside the contact hole and on an exposed conductive pattern inside the contact hole and on a sidewall of the contact hole and a metal layer can be formed on the conductive layer to fill the contact hole.

摘要翻译： 在半导体器件中形成金属布线的方法可以包括在形成在绝缘层中的接触孔之外形成蚀刻停止层，并避免在接触孔内形成蚀刻停止层。 可以在接触孔外部的蚀刻停止层上形成导电层，并且在接触孔内部和接触孔的侧壁上的暴露的导电图案上形成导电层，并且可以在导电层上形成金属层以填充接触孔。

公开(公告)号：US20090325371A1

公开(公告)日：2009-12-31

申请号：US12424922

申请日：2009-04-16

申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

IPC分类号： H01L21/28

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

摘要翻译： 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。