公开(公告)号：US06864735B2

公开(公告)日：2005-03-08

申请号：US10665175

申请日：2003-09-18

Applicant: Jin-tae Joo

Inventor： Jin-tae Joo

IPC: G06F1/04 ,  G06F1/10 ,  G06F1/24 ,  G11C7/00

CPC classification number: G06F1/24 ,  G06F1/10

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract translation: 提供一种用于再生复位和时钟信号的装置和方法以及使用该装置和方法的高速数字系统。 在本发明的再生电路中，时钟电路接收外部时钟信号，并从内部时钟信号产生，该内部时钟信号被转发到多个时钟电路，例如D触发器。 复位电路接收外部复位信号并由其产生内部复位信号，该内部复位信号被转发到时钟电路以复位时钟电路。 时钟屏蔽电路屏蔽内部时钟信号以进行掩蔽周期，使得时钟电路在屏蔽周期期间不被计时。 本发明的高速数字系统包括耦合在总线上的多个功能块。 本发明的复位和时钟再生电路从外部施加的复位和时钟信号产生内部复位和时钟信号。

公开(公告)号：US06868118B2

公开(公告)日：2005-03-15

申请号：US09794800

申请日：2001-02-27

Applicant: Jin-tae Joo

Inventor： Jin-tae Joo

IPC: H04J11/00 ,  H04L1/00 ,  H04L5/02 ,  H04L7/08 ,  H04L25/03 ,  H04L27/00 ,  H04L27/26 ,  H04B1/38

CPC classification number: H04L27/2614 ,  H04L1/0001 ,  H04L5/023 ,  H04L25/03012 ,  H04L25/03159 ,  H04L27/2607 ,  H04L27/2656 ,  H04L27/2678 ,  H04L2025/03414 ,  H04L2025/03522

Abstract: A discrete multi-tone (DMT) processor receives predetermined control signals from a digital signal processor (DSP) within an asymmetric digital subscriber line (ADSL) modem, modulates transmission data in response to the control signals, and demodulates reception data. The DMT processor includes a frame synchronization signal generator, a transmitter, and a receiver. The frame synchronization generator generates a transmission frame synchronization signal and a reception frame synchronization signal in response to a cyclic prefix contained in the transmission data or reception data and a reception synchronization shift signal applied from the DSP. The transmitter DMT modulates and gain-controls the transmission data input in response to the transmission frame synchronization signal The receiver gain-controls and DMT demodulates the reception data response to the reception frame synchronization.

Abstract translation: 离散多音（DMT）处理器从非对称数字用户线（ADSL）调制解调器内的数字信号处理器（DSP）接收预定的控制信号，响应于控制信号调制发送数据，并对接收数据进行解调。 DMT处理器包括帧同步信号发生器，发射机和接收机。 帧同步发生器响应包含在发送数据或接收数据中的循环前缀以及从DSP施加的接收同步移位信号，生成发送帧同步信号和接收帧同步信号。 发射机DMT响应于传输帧同步信号调制和增益控制传输数据输入。接收机增益控制和DMT解调接收帧同步的接收数据响应。