公开(公告)号：US07315583B2

公开(公告)日：2008-01-01

申请号：US10408512

申请日：2003-04-07

Applicant: Jin-Tae Joo

Inventor： Jin-Tae Joo

IPC: H03K9/00

CPC classification number: H04L49/901 ,  H04L27/2601 ,  H04L49/90 ,  H04L49/9042 ,  H04L67/34 ,  H04L69/329 ,  H04M11/062

Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract translation: 本发明提供了包括离散多音（DMT）调制解调器模块的非对称数字用户线（ADSL）调制解调器。 DMT调制解调器模块包括数字信号处理器（DSP），其被配置为处理用于在与主机设备相关联的安装期间初始化ADSL调制解调器的控制信号，并将处理的控制信号发送到主机设备的主机控制器。

公开(公告)号：US06864735B2

公开(公告)日：2005-03-08

申请号：US10665175

申请日：2003-09-18

Applicant: Jin-tae Joo

Inventor： Jin-tae Joo

IPC: G06F1/04 ,  G06F1/10 ,  G06F1/24 ,  G11C7/00

CPC classification number: G06F1/24 ,  G06F1/10

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract translation: 提供一种用于再生复位和时钟信号的装置和方法以及使用该装置和方法的高速数字系统。 在本发明的再生电路中，时钟电路接收外部时钟信号，并从内部时钟信号产生，该内部时钟信号被转发到多个时钟电路，例如D触发器。 复位电路接收外部复位信号并由其产生内部复位信号，该内部复位信号被转发到时钟电路以复位时钟电路。 时钟屏蔽电路屏蔽内部时钟信号以进行掩蔽周期，使得时钟电路在屏蔽周期期间不被计时。 本发明的高速数字系统包括耦合在总线上的多个功能块。 本发明的复位和时钟再生电路从外部施加的复位和时钟信号产生内部复位和时钟信号。

公开(公告)号：US06288746B1

公开(公告)日：2001-09-11

申请号：US09120177

申请日：1998-07-22

Applicant: Jin-Tae Joo

Inventor： Jin-Tae Joo

IPC: H04N1120

CPC classification number: H04N7/0135 ,  G06T3/4007 ,  G09G5/00 ,  G09G5/02 ,  G09G2340/0414 ,  G09G2340/0421 ,  H04N5/14 ,  H04N9/64 ,  H04N9/642

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system. The apparatus includes an analog-to-digital converting unit for sampling original color signals at predetermined intervals and converting the sampled signals into digital signals; a color-space converting unit for converting a digital signal of the analog-to-digital converting unit into a brightness signal and a color tone signal and for outputting these signals; a storage unit for storing a look-up table representing linear interpolation coefficients converted in response to a conversion of an image size; a horizontal scaling unit for linearly interpolating one cycle of the brightness signal and color tone signal in response to a conversion of image size with reference to the look-up table of the storage unit, and for horizontally scaling by repeatedly outputting the outcome linearly-interpolated; a line memory unit for momentarily storing a horizontally scaled signal by the horizontal scaling unit; a vertical scaling unit for interpolating a cycle of a horizontal scaling signal provided by the line memory unit in response to the conversion of the image size with reference to the look-up table, thereby vertically scaling by repeatedly outputting the linearly interpolated data; and a frame memory unit for storing signals vertically and horizontally-scaled by the vertical scaling unit and for converting vertical and horizontal frequencies of the vertical and horizontal scaled signals.

Abstract translation: 一种用于在视频信号处理系统中转换图像格式及其方法的装置。 该装置包括用于以预定间隔对原始颜色信号进行采样并将采样信号转换为数字信号的模数转换单元; 色空间转换单元，用于将模数转换单元的数字信号转换成亮度信号和色调信号并输出​​这些信号; 存储单元，用于存储表示响应于图像大小的转换而转换的线性内插系数的查找表; 水平缩放单元，用于响应于参考存储单元的查找表的图像尺寸的转换来线性内插亮度信号和色调信号的一个周期，并且通过重复地输出线性内插的结果来水平缩放 ; 行存储单元，用于通过水平缩放单元暂时存储水平缩放信号; 垂直缩放单元，用于响应于参考查找表的图像大小的转换来内插由行存储器单元提供的水平缩放信号的周期，从而通过重复输出线性内插数据进行垂直缩放; 以及帧存储单元，用于存储由垂直缩放单元垂直和水平缩放的信号，并用于转换垂直和水平缩放信号的垂直和水平频率。

公开(公告)号：US07574638B2

公开(公告)日：2009-08-11

申请号：US11345897

申请日：2006-02-02

Applicant: Hae-Jin Song ,  Jin-Tae Joo

Inventor： Hae-Jin Song ,  Jin-Tae Joo

IPC: G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31725

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.

Abstract translation: 本发明提供能够使用一个测试引脚进行测试并且使用没有任何测试引脚的输入/输出引脚的半导体器件及其测试方法。 一个半导体器件包括用于输入/输出测试数据的测试引脚，用于响应于外部复位信号和时钟信号激活使能信号的操作模式控制器，用于通过所述时钟信号接收与时钟信号同步的串行数据的操作模式存储器 测试引脚以及响应于存储在操作模式存储器中的串行数据产生操作模式选择信号的操作模式解码器。 另一个半导体器件包括用于接收测试数据的输入/输出引脚，用于延迟复位信号的延迟复位信号发生器，响应于复位信号计数时钟信号的计数器以产生计数值;模式寄存器， 测试数据和用于向模式寄存器产生选择信号的解码器，以指定写入测试数据的模式寄存器中的位置。

公开(公告)号：US06757026B2

公开(公告)日：2004-06-29

申请号：US09841252

申请日：2001-04-25

Applicant: Jin-Tae Joo

Inventor： Jin-Tae Joo

IPC: H04N701

CPC classification number: H04N7/0135 ,  G06T3/4007 ,  G09G5/00 ,  G09G5/02 ,  G09G2340/0414 ,  G09G2340/0421 ,  H04N5/14 ,  H04N9/64 ,  H04N9/642

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system. The apparatus includes an analog-to-digital converting unit for sampling original color signals at predetermined intervals and converting the sampled signals into digital signals; a color-space converting unit for converting a digital signal of the analog-to-digital converting unit into a brightness signal and a color tone signal and for outputting these signals; a storage unit for storing a look-up table representing linear interpolation coefficients converted in response to a conversion of an image size; a horizontal scaling unit for linearly interpolating one cycle of the brightness signal and color tone signal in response to a conversion of image size with reference to the look-up table of the storage unit, and for horizontally scaling by repeatedly outputting the outcome linearly-interpolated; a line memory unit for momentarily storing a horizontally scaled signal by the horizontal scaling unit; a vertical scaling unit for interpolating a cycle of a horizontal scaling signal provided by the line memory unit in response to the conversion of the image size with reference to the look-up table, thereby vertically scaling by repeatedly outputting the linearly interpolated data; and a frame memory unit for storing signals vertically and horizontally-scaled by the vertical scaling unit and for converting vertical and horizontal frequencies of the vertical and horizontal scaled signals.

Abstract translation: 一种用于在视频信号处理系统中转换图像格式及其方法的装置。 该装置包括用于以预定间隔对原始颜色信号进行采样并将采样信号转换为数字信号的模数转换单元; 色空间转换单元，用于将模数转换单元的数字信号转换成亮度信号和色调信号并输出​​这些信号; 存储单元，用于存储表示响应于图像大小的转换而转换的线性内插系数的查找表; 水平缩放单元，用于响应于参考存储单元的查找表的图像尺寸的转换来线性内插亮度信号和色调信号的一个周期，并且通过重复地输出线性内插的结果来水平缩放 ; 行存储单元，用于通过水平缩放单元暂时存储水平缩放信号; 垂直缩放单元，用于响应于参考查找表的图像大小的转换来内插由行存储器单元提供的水平缩放信号的周期，从而通过重复输出线性内插数据进行垂直缩放; 以及帧存储单元，用于存储由垂直缩放单元垂直和水平缩放的信号，并用于转换垂直和水平缩放信号的垂直和水平频率。

公开(公告)号：US06868118B2

公开(公告)日：2005-03-15

申请号：US09794800

申请日：2001-02-27

Applicant: Jin-tae Joo

Inventor： Jin-tae Joo

IPC: H04J11/00 ,  H04L1/00 ,  H04L5/02 ,  H04L7/08 ,  H04L25/03 ,  H04L27/00 ,  H04L27/26 ,  H04B1/38

CPC classification number: H04L27/2614 ,  H04L1/0001 ,  H04L5/023 ,  H04L25/03012 ,  H04L25/03159 ,  H04L27/2607 ,  H04L27/2656 ,  H04L27/2678 ,  H04L2025/03414 ,  H04L2025/03522

Abstract: A discrete multi-tone (DMT) processor receives predetermined control signals from a digital signal processor (DSP) within an asymmetric digital subscriber line (ADSL) modem, modulates transmission data in response to the control signals, and demodulates reception data. The DMT processor includes a frame synchronization signal generator, a transmitter, and a receiver. The frame synchronization generator generates a transmission frame synchronization signal and a reception frame synchronization signal in response to a cyclic prefix contained in the transmission data or reception data and a reception synchronization shift signal applied from the DSP. The transmitter DMT modulates and gain-controls the transmission data input in response to the transmission frame synchronization signal The receiver gain-controls and DMT demodulates the reception data response to the reception frame synchronization.

Abstract translation: 离散多音（DMT）处理器从非对称数字用户线（ADSL）调制解调器内的数字信号处理器（DSP）接收预定的控制信号，响应于控制信号调制发送数据，并对接收数据进行解调。 DMT处理器包括帧同步信号发生器，发射机和接收机。 帧同步发生器响应包含在发送数据或接收数据中的循环前缀以及从DSP施加的接收同步移位信号，生成发送帧同步信号和接收帧同步信号。 发射机DMT响应于传输帧同步信号调制和增益控制传输数据输入。接收机增益控制和DMT解调接收帧同步的接收数据响应。

公开(公告)号：US5913229A

公开(公告)日：1999-06-15

申请号：US766461

申请日：1996-12-12

Applicant: Jin-Tae Joo

Inventor： Jin-Tae Joo

IPC: G06F5/10 ,  G06F12/04 ,  G06F9/12

CPC classification number: G06F5/10 ,  G06F12/04

Abstract: A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data is sequentially stored head to tail so that memory space is not wasted. The buffer memory controller includes: a sample pointer reading unit providing word addresses indicating the word position where the samples start, and a bit address indicating a bit position where the sample starts; a word shift register receiving data corresponding to the word addresses from the buffer memory, shifting the inputted data by the specific bit according to maximum assignable word, and outputting data of maximum assignable bit; a barrel shifter receiving the output of the shift register, shifting the inputted data by the bit address, and outputting the shifted data as maximum sample bit; and a masking circuit for inputting an output of the barrel shifter, masking the inputted data with mask data in accordance with each bit corresponding to the sample, and outputting the masked data as the maximum sample bit.

Abstract translation: 缓冲存储器控制器允许顺序地存储具有可变位长度的采样数据。 也就是说，不是将每个采样的数据分配给存储器的单个字，而是将采样的数据顺序地存储在尾部，使得不会浪费存储器空间。 缓冲存储器控制器包括：采样指针读取单元，其提供指示采样开始的字位置的字地址，以及指示采样开始的位位置的位地址; 字移位寄存器，从缓冲存储器接收对应于字地址的数据，根据最大可指定字移位输入数据特定位，并输出最大可分配位的数据; 接收移位寄存器的输出的桶形移位器，将输入的数据移位位地址，并输出移位数据作为最大取样位; 以及屏蔽电路，用于输入桶形移位器的输出，根据与样本相对应的每个位掩蔽输入的数据，并输出掩蔽的数据作为最大采样位。

公开(公告)号：US20060184847A1

公开(公告)日：2006-08-17

申请号：US11345897

申请日：2006-02-02

Applicant: Hae-Jin Song ,  Jin-Tae Joo

Inventor： Hae-Jin Song ,  Jin-Tae Joo

IPC: G01R31/28

CPC classification number: G01R31/3172 ,  G01R31/31723 ,  G01R31/31725

Abstract: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.