公开(公告)号：US20070173026A1

公开(公告)日：2007-07-26

申请号：US11336899

申请日：2006-01-23

申请人： JinChuan Zeng ,  Chong Ren ,  Bin Qiu ,  Xian-Feng Liu

发明人： JinChuan Zeng ,  Chong Ren ,  Bin Qiu ,  Xian-Feng Liu

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/0658 ,  H01L21/8224 ,  H01L27/067 ,  H01L27/0682 ,  H01L27/0821 ,  H01L28/20

摘要： The present invention discloses a method for fabricating bipolar integrated circuits, wherein LOCOS technology is used to define the active regions needed by all elements so that the self-alignment of the associated layers can be realized, and implant resistor regions are also directly defined in the active regions by local oxide layers; after base regions have been driven in the wafer, the resistors are implanted into the wafer so that the cost of resistor photomasks can be saved; silicon nitride is adopted to be the material of the dielectric layers of the capacitors, and with the characteristic of a buffering oxide etchant that etches oxide faster than it etches silicon nitride, the conventional deposition sequence of the dielectric layer is changed so that the formation of the dielectric layer needs only a single photomask.

摘要翻译： 本发明公开了一种用于制造双极集成电路的方法，其中使用LOCOS技术来定义所有元件所需的有源区域，从而可以实现相关层的自对准，注入电阻器区域也直接限定在 活性区域由局部氧化物层; 在晶圆驱动基极区之后，将电阻注入到晶片中，从而可以节省电阻光掩模的成本; 采用氮化硅作为电容器的电介质层的材料，并且具有缓蚀氧化物蚀刻剂的特性，其蚀刻氧化物比其刻蚀氮化硅更快，介电层的常规沉积顺序发生变化，从而形成 电介质层仅需要一个光掩模。

公开(公告)号：US20060118881A1

公开(公告)日：2006-06-08

申请号：US11335623

申请日：2006-01-20

申请人： Chong Ren ,  Xian-Feng Liu ,  Bin Qiu

发明人： Chong Ren ,  Xian-Feng Liu ,  Bin Qiu

IPC分类号： H01L29/76

CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/735

摘要： The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

摘要翻译： 本发明涉及一种横向PNP晶体管及其制造方法。 在掺杂发射极区域和集电极区域形成之前，首先引入介质掺杂的N型基极区域和掺杂光的P 集电极区域。 LPNP的横向和底部宽度的发射极 - 基极 - 集电极掺杂分布类似于NPN。 设计人员可以根据LPNP晶体管的电流增益（Hfe），集电极 - 基极击穿电压（BVceo）和早期电压（VA）的要求，优化各个区域的掺杂特性和面积。 这些优点可能导致LPNP晶体管的面积减小和性能的提高。

公开(公告)号：US07446012B2

公开(公告)日：2008-11-04

申请号：US11335623

申请日：2006-01-20

申请人： Chong Ren ,  Xian-Feng Liu ,  Bin Qiu

发明人： Chong Ren ,  Xian-Feng Liu ,  Bin Qiu

IPC分类号： H01L21/265 ,  H01L29/72

CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/735

摘要： The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

摘要翻译： 本发明涉及一种横向PNP晶体管及其制造方法。 在掺杂发射极区域和集电极区域形成之前，首先引入介质掺杂的N型基极区域和掺杂光的P 集电极区域。 LPNP的横向和底部宽度的发射极 - 基极 - 集电极掺杂分布类似于NPN。 设计人员可以根据LPNP晶体管的电流增益（Hfe），集电极 - 基极击穿电压（BVceo）和早期电压（VA）的要求，优化各个区域的掺杂特性和面积。 这些优点可能导致LPNP晶体管的面积减小和性能的提高。

公开(公告)号：US20070176254A1

公开(公告)日：2007-08-02

申请号：US11341493

申请日：2006-01-30

申请人： Xian-Feng Liu ,  Chong Ren ,  Jin-Chuan Zeng ,  Bin Qiu

发明人： Xian-Feng Liu ,  Chong Ren ,  Jin-Chuan Zeng ,  Bin Qiu

IPC分类号： H01L29/00

CPC分类号： H01L29/7375 ,  H01L27/0652 ,  H01L27/067 ,  H01L27/0676 ,  H01L29/66143 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/872 ,  H01L29/92 ,  H01L29/94

摘要： The present invention discloses a high voltage and high frequency poly emitter bipolar structure with improved breakdown voltage performance. The advantage of the poly emitter bipolar structures is that the SOD coating layer can improve the breakdown voltage of a capacitor structure higher to be 6-8 volts. In addition, the poly emitter bipolar structure having the inter-level dielectric layer deposited by PECVD on the emitter and collector by optimizing PECVD deposition process condition to adjust the charge in the oxide of inter-level dielectric layer has a breakdown voltage higher than 30 volts.

摘要翻译： 本发明公开了具有改进的击穿电压性能的高压和高频多晶硅发射极双极结构。 多晶硅发射极双极结构的优点在于，SOD涂层可以提高电容器结构的击穿电压，高于6-8伏特。 此外，通过优化PECVD沉积工艺条件来调节电介质层的氧化物中的电荷，通过PECVD在发射极和集电极上沉积的层间电介质层的多晶硅发射极双极结构具有高于30伏的击穿电压 。

公开(公告)号：US07544558B2

公开(公告)日：2009-06-09

申请号：US11373278

申请日：2006-03-13

申请人： Chong Ren ,  Xian-Feng Liu ,  Huang Hai Tao

发明人： Chong Ren ,  Xian-Feng Liu ,  Huang Hai Tao

IPC分类号： H01L21/20

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/8249 ,  H01L27/0623

摘要： This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

摘要翻译： 本发明是在门极多层之前的CMOS活性层之后形成DMOS通道，使模块化DMOS工艺步骤容易地添加到亚微米CMOS或BiCMOS工艺中。 并且DMOS源由通过与DMOS体的窗口自对准的间隔分隔的植入物形成。 通过这种方法，CMOS和双极器件的性能形成了原来的CMOS或BiCMOS工艺不变。 产品设计套件，如CMOS和BiCMOS的标准单元库，可以连续使用，无变化。

公开(公告)号：US20070212823A1

公开(公告)日：2007-09-13

申请号：US11373278

申请日：2006-03-13

申请人： Chong Ren ,  Xian-Feng Liu ,  Huang Tao

发明人： Chong Ren ,  Xian-Feng Liu ,  Huang Tao

IPC分类号： H01L21/8232

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/8249 ,  H01L27/0623

摘要： This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

摘要翻译： 本发明是在门极多层之前的CMOS活性层之后形成DMOS通道，使模块化DMOS工艺步骤容易地添加到亚微米CMOS或BiCMOS工艺中。 并且DMOS源由通过与DMOS体的窗口自对准的间隔分隔的植入物形成。 通过这种方法，CMOS和双极器件的性能形成了原来的CMOS或BiCMOS工艺不变。 产品设计套件，如CMOS和BiCMOS的标准单元库，可以连续使用，无变化。

公开(公告)号：US07535058B2

公开(公告)日：2009-05-19

申请号：US11785867

申请日：2007-04-20

申请人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

发明人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

IPC分类号： H01L29/735

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66689

摘要： A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

摘要翻译： 横向DMOS结构包括在漏极侧的栅极下方和附近的掺杂磷的p型区域。 栅极附近表面的电场减小。 因此，栅极附近的电场减小，侧向DMOS器件的SOA（安全工作区）增加，时间可靠性提高。 此外，本发明的横向DMOS可以在不增加制造成本的情况下制造。

公开(公告)号：US20070278569A1

公开(公告)日：2007-12-06

申请号：US11785867

申请日：2007-04-20

申请人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

发明人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66689

摘要： A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

摘要翻译： 横向DMOS结构包括在漏极侧的栅极下方和附近的掺杂磷的p型区域。 栅极附近表面的电场减小。 因此，栅极附近的电场减小，侧向DMOS器件的SOA（安全工作区）增加，时间可靠性提高。 此外，本发明的横向DMOS可以在不增加制造成本的情况下制造。

公开(公告)号：US20060148188A1

公开(公告)日：2006-07-06

申请号：US11028666

申请日：2005-01-05

申请人： Xian Liu ,  Chong Ren ,  Bin Qiu ,  Xu Xu

发明人： Xian Liu ,  Chong Ren ,  Bin Qiu ,  Xu Xu

IPC分类号： H01L21/8222

CPC分类号： H01L27/0658

摘要： A fabrication method is applied to the bipolar integrated circuit, which combines with various patterns of the masks using in the different processes to form a combination mask. By using the combination mask, a silicon dioxide layer is etched to produce the open windows required in the different processes. Thereafter, according to the requirements of different processes, the unused windows are covered with photoresists to avoid the alignment errors resulted from the pattering and etching of different masks. Because the method doesn't need to reserve tolerance for alignment errors, the degree of integration of the semiconductor processes is enhanced and the cost of production is reduced.

摘要翻译： 一种制造方法应用于双极集成电路，其结合了在不同工艺中使用的掩模的各种图案以形成组合掩模。 通过使用组合掩模，蚀刻二氧化硅层以产生不同工艺中所需的开放窗口。 此后，根据不同过程的要求，未使用的窗口被光致抗蚀剂覆盖，以避免不同掩模的图案和蚀刻产生的对准误差。 由于该方法不需要对准误差的预留容差，所以提高了半导体工艺的集成度，降低了生产成本。

公开(公告)号：US20060043528A1

公开(公告)日：2006-03-02

申请号：US10930851

申请日：2004-09-01

申请人： Chong Ren ,  Xian Liu ,  Bin Qiu

发明人： Chong Ren ,  Xian Liu ,  Bin Qiu

IPC分类号： H01L27/082

CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/735

摘要： The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and Early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

摘要翻译： 本发明涉及一种横向PNP晶体管及其制造方法。 在掺杂发射极区域和集电极区域形成之前，首先引入介质掺杂的N型基极区域和掺杂光的P 集电极区域。 LPNP的横向和底部宽度的发射极 - 基极 - 集电极掺杂分布类似于NPN。 根据当前增益（Hfe），集电极基极击穿电压（BVceo）和LPNP晶体管的早期电压（VA）的要求，设计人员可以优化各个区域的掺杂特性和面积。 这些优点可能导致LPNP晶体管的面积减小和性能的提高。