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    HEAT SINK HAVING HEAT PIPE PROTECTION MECHANISM
    1.
    发明申请
    HEAT SINK HAVING HEAT PIPE PROTECTION MECHANISM 审中-公开
    热管热管保护机制

    公开(公告)号：US20130153175A1

    公开(公告)日：2013-06-20

    申请号：US13566100

    申请日：2012-08-03

    申请人： Chong-Ren LIN

    发明人： Chong-Ren LIN

    IPC分类号： F28D15/04

    CPC分类号： H05K7/20318 ,  F28D15/0233 ,  F28D15/0275 ,  F28F1/32 ,  F28F19/06 ,  F28F2265/02 ,  H01L23/3672 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A heat sink having a heat pipe protection mechanism includes a heat pipe, a metallic sleeve and a plurality of heat-dissipating fins. The heat pipe has an evaporating section and a condensing section. The evaporating section is combined with a heat-dissipating base. The metallic sleeve has a closed end and an open end opposite to the closed end. The condensing section is disposed through the open end of the metallic sleeve. Each of the heat-dissipating fins has a through-hole corresponding to the heat pipe. The metallic sleeve having the condensing section disposed therein is fitted in the through-hole. By this arrangement, the condensing section is completely separated from the outside, so that the heat pipe can be protected from suffering damage due to external impacts or getting rusty. Thus, the lifetime of the heat pipe is maintained, and the frequency of repairing the heat sink is reduced.

    摘要翻译： 具有热管保护机构的散热器包括热管，金属套和多个散热片。 热管具有蒸发部和冷凝部。 蒸发段与散热基底结合。 金属套筒具有封闭端和与封闭端相对的开口端。 冷凝部分穿过金属套筒的开口端。 每个散热翅片具有对应于热管的通孔。 具有设置在其中的冷凝部的金属套筒嵌合在通孔中。 通过这种布置，冷凝部分与外部完全分开，从而可以保护热管免受外部冲击或生锈的损坏。 因此，保持热管的寿命，并且减少了修理散热器的频率。

    Method for integrating DMOS into sub-micron CMOS process
    2.
    发明授权
    Method for integrating DMOS into sub-micron CMOS process 有权
    将DMOS集成到亚微米CMOS工艺中的方法

    公开(公告)号：US07544558B2

    公开(公告)日：2009-06-09

    申请号：US11373278

    申请日：2006-03-13

    申请人： Chong Ren ,  Xian-Feng Liu ,  Huang Hai Tao

    发明人： Chong Ren ,  Xian-Feng Liu ,  Huang Hai Tao

    IPC分类号： H01L21/20

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/8249 ,  H01L27/0623

    摘要： This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

    摘要翻译： 本发明是在门极多层之前的CMOS活性层之后形成DMOS通道，使模块化DMOS工艺步骤容易地添加到亚微米CMOS或BiCMOS工艺中。 并且DMOS源由通过与DMOS体的窗口自对准的间隔分隔的植入物形成。 通过这种方法，CMOS和双极器件的性能形成了原来的CMOS或BiCMOS工艺不变。 产品设计套件，如CMOS和BiCMOS的标准单元库，可以连续使用，无变化。

    Method of manufacturing solder mask of printed circuit board
    3.
    发明授权
    Method of manufacturing solder mask of printed circuit board 失效
    制造印刷电路板的焊接掩模的方法

    公开(公告)号：US07080447B2

    公开(公告)日：2006-07-25

    申请号：US10800648

    申请日：2004-03-16

    申请人： Chong-Ren Maa ,  Wan-Kuo Chih ,  Ming-Sung Tsai

    发明人： Chong-Ren Maa ,  Wan-Kuo Chih ,  Ming-Sung Tsai

    IPC分类号： H05K3/02

    CPC分类号： H05K3/0041 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/28 ,  H05K2201/0191 ,  H05K2201/0959 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0554 ,  H05K2203/066 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.

    摘要翻译： 一种适于在电路板的基板的表面上施加焊接掩模的焊接掩模制造方法，所述表面设置有具有未被覆盖部分的导体图案和被所述焊接掩模覆盖的遮蔽部分。 该方法包括以下步骤：a）在所述基板的表面上设置具有与所述基板的基本上相同的膨胀系数的半固体焊料掩模材料层以覆盖所述铜导体图案，以及覆盖所述铜导体图案的金属箔 材料层; b）向金属箔施加压力并施加烘烤处理以将焊接掩模材料固化成固体; c）利用化学溶液和等离子体蚀刻分别去除所述铜导体图案的未加盖部分上方的金属箔和固体焊料掩模材料，使得未加盖的部分可以暴露; 和d）使用化学溶液去除残留的金属箔。

    Lateral DMOS structure
    5.
    发明授权
    Lateral DMOS structure 有权
    侧向DMOS结构

    公开(公告)号：US07535058B2

    公开(公告)日：2009-05-19

    申请号：US11785867

    申请日：2007-04-20

    申请人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

    发明人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

    IPC分类号： H01L29/735

    CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66689

    摘要： A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

    摘要翻译： 横向DMOS结构包括在漏极侧的栅极下方和附近的掺杂磷的p型区域。 栅极附近表面的电场减小。 因此，栅极附近的电场减小，侧向DMOS器件的SOA（安全工作区）增加，时间可靠性提高。 此外，本发明的横向DMOS可以在不增加制造成本的情况下制造。

    Lateral DMOS structure
    6.
    发明申请
    Lateral DMOS structure 有权
    侧向DMOS结构

    公开(公告)号：US20070278569A1

    公开(公告)日：2007-12-06

    申请号：US11785867

    申请日：2007-04-20

    申请人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

    发明人： Xian-Feng Liu ,  Chong Ren ,  Hai-Tao Huang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66689

    摘要： A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

    摘要翻译： 横向DMOS结构包括在漏极侧的栅极下方和附近的掺杂磷的p型区域。 栅极附近表面的电场减小。 因此，栅极附近的电场减小，侧向DMOS器件的SOA（安全工作区）增加，时间可靠性提高。 此外，本发明的横向DMOS可以在不增加制造成本的情况下制造。

    BIMETAL LAYER MANUFACTURING METHOD
    7.
    发明申请
    BIMETAL LAYER MANUFACTURING METHOD 有权
    双层制造方法

    公开(公告)号：US20050260852A1

    公开(公告)日：2005-11-24

    申请号：US10851177

    申请日：2004-05-24

    申请人： Hiu Ip ,  Ellick Ma ,  Yan Yu ,  Chong Ren ,  Ji-Wei Sun

    发明人： Hiu Ip ,  Ellick Ma ,  Yan Yu ,  Chong Ren ,  Ji-Wei Sun

    IPC分类号： H01L21/02 ,  H01L29/76

    CPC分类号： H01L28/40 ,  Y10S438/957

    摘要： A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.

    摘要翻译： 双金属层制造方法包括以下步骤：在半导体衬底的表面上形成第一电介质层，所述第一电介质层具有形成在其上的选定图案的第一金属层（导电层）; 在第一介电层的表面上形成SOG层; 形成第二电介质层; 在上述层上形成所需的通孔，直到到达第一金属层; 通过PECVD从电介质材料形成线性层; 通过各向异性等离子体蚀刻工艺从选定位置去除不需要的线性层; 最终在要形成MIM电容器的线性层的选定表面上形成第二金属层，并且在通孔中形成连接插塞，而不产生通孔毒药。

    Method for integrating DMOS into sub-micron CMOS process
    10.
    发明申请
    Method for integrating DMOS into sub-micron CMOS process 有权
    将DMOS集成到亚微米CMOS工艺中的方法

    公开(公告)号：US20070212823A1

    公开(公告)日：2007-09-13

    申请号：US11373278

    申请日：2006-03-13

    申请人： Chong Ren ,  Xian-Feng Liu ,  Huang Tao

    发明人： Chong Ren ,  Xian-Feng Liu ,  Huang Tao

    IPC分类号： H01L21/8232

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/8249 ,  H01L27/0623

    摘要： This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

    摘要翻译： 本发明是在门极多层之前的CMOS活性层之后形成DMOS通道，使模块化DMOS工艺步骤容易地添加到亚微米CMOS或BiCMOS工艺中。 并且DMOS源由通过与DMOS体的窗口自对准的间隔分隔的植入物形成。 通过这种方法，CMOS和双极器件的性能形成了原来的CMOS或BiCMOS工艺不变。 产品设计套件，如CMOS和BiCMOS的标准单元库，可以连续使用，无变化。