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    Compensation Techniques for Reducing Power Consumption in Digital Circuitry
    4.
    发明申请
    Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
    降低数字电路功耗的补偿技术

    公开(公告)号：US20100244937A1

    公开(公告)日：2010-09-30

    申请号：US12160373

    申请日：2007-10-31

    申请人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： G05F1/10

    CPC分类号： H03K19/00369

    摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

    摘要翻译： 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。

    Compensation techniques for reducing power consumption in digital circuitry
    8.
    发明授权
    Compensation techniques for reducing power consumption in digital circuitry 有权
    用于降低数字电路功耗的补偿技术

    公开(公告)号：US07965133B2

    公开(公告)日：2011-06-21

    申请号：US12160373

    申请日：2007-10-31

    申请人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： G05F1/10

    CPC分类号： H03K19/00369

    摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

    摘要翻译： 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。

    Method and apparatus for digital VCDL startup
    9.
    发明授权
    Method and apparatus for digital VCDL startup 失效
    数字VCDL启动的方法和装置

    公开(公告)号：US08219344B2

    公开(公告)日：2012-07-10

    申请号：US12789544

    申请日：2010-05-28

    申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Paul H. Tracy

    发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Paul H. Tracy

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

    摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。