公开(公告)号：US07598161B2

公开(公告)日：2009-10-06

申请号：US11861534

申请日：2007-09-26

申请人： Jingrong Zhou ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Akif Sultan

发明人： Jingrong Zhou ,  Mark Michael ,  David Wu ,  James F. Buller ,  Akif Sultan

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

摘要翻译： 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

申请人： Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

发明人： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC分类号： G06F17/50 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/78 ,  H01L29/7843

摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

摘要翻译： 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US07638837B2

公开(公告)日：2009-12-29

申请号：US11861051

申请日：2007-09-25

申请人： Akif Sultan ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu

发明人： Akif Sultan ,  Mark Michael ,  David Wu

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

摘要翻译： 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US06727136B1

公开(公告)日：2004-04-27

申请号：US10273291

申请日：2002-10-18

申请人： James F. Buller ,  Derick J. Wristers ,  David Wu ,  Akif Sultan

发明人： James F. Buller ,  Derick J. Wristers ,  David Wu ,  Akif Sultan

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.

摘要翻译： 一种制造半导体器件的方法，包括以下顺序的步骤：（a）提供半导体衬底，该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和（b）将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中，以在其中形成含有掺杂剂的区域，其中接合部的深度基本上等于预先 - 选择的厚度，其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散，从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。

公开(公告)号：US08329519B2

公开(公告)日：2012-12-11

申请号：US13305449

申请日：2011-11-28

申请人： Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

发明人： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC分类号： H01L27/12

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

摘要翻译： 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US08134208B2

公开(公告)日：2012-03-13

申请号：US11861928

申请日：2007-09-26

申请人： Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

发明人： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC分类号： H01L27/12

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

摘要翻译： 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US20120007182A1

公开(公告)日：2012-01-12

申请号：US13239865

申请日：2011-09-22

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L27/12

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。

公开(公告)号：US08048753B2

公开(公告)日：2011-11-01

申请号：US12483737

申请日：2009-06-12

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。

公开(公告)号：US20100314685A1

公开(公告)日：2010-12-16

申请号：US12483737

申请日：2009-06-12

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L27/06 ,  H01L21/77

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。

公开(公告)号：US08546855B2

公开(公告)日：2013-10-01

申请号：US13239865

申请日：2011-09-22

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。