公开(公告)号：US20170200736A1

公开(公告)日：2017-07-13

申请号：US15349084

申请日：2016-11-11

申请人： Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

发明人： Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L27/11582 ,  H01L21/76879 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/0649

摘要： A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.

公开(公告)号：US20170062472A1

公开(公告)日：2017-03-02

申请号：US15249590

申请日：2016-08-29

申请人： Joyoung PARK ,  HAUK HAN ,  SEOK-WON LEE ,  JEONGGIL LEE ,  JINWOO PARK ,  KlHYUN YOON ,  HYUNSEOK LIM ,  JOOYEON HA

发明人： Joyoung PARK ,  HAUK HAN ,  SEOK-WON LEE ,  JEONGGIL LEE ,  JINWOO PARK ,  KlHYUN YOON ,  HYUNSEOK LIM ,  JOOYEON HA

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

摘要： Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

摘要翻译： 公开了一种半导体存储器件，其包括在衬底上的堆叠，通过每个堆叠连接到衬底的垂直沟道部分以及布置在堆叠之间的分离图案。 每个堆叠可以包括堆叠在基板上的多个栅电极和插在栅电极之间的绝缘图案。 每个栅电极可以包括第一金属图案，其布置在绝缘图案之间以限定朝向垂直沟道部分凹陷的凹陷区域和设置在凹部区域中的第二金属图案。 第一和第二金属图案可以包含相同的金属材料，并且可以具有彼此不同的平均晶粒尺寸。