公开(公告)号：US20170179149A1

公开(公告)日：2017-06-22

申请号：US15241781

申请日：2016-08-19

申请人： JOYOUNG PARK ,  YONG-HYUN KWON ,  JEONGSOO KIM ,  SEOK-WON LEE ,  JINWOO PARK ,  OIK KWON ,  SEUNGPIL CHUNG

发明人： JOYOUNG PARK ,  YONG-HYUN KWON ,  JEONGSOO KIM ,  SEOK-WON LEE ,  JINWOO PARK ,  OIK KWON ,  SEUNGPIL CHUNG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575

摘要： A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

公开(公告)号：US09953997B2

公开(公告)日：2018-04-24

申请号：US15249590

申请日：2016-08-29

申请人： Joyoung Park ,  Hauk Han ,  Seok-Won Lee ,  Jeonggil Lee ,  Jinwoo Park ,  Kihyun Yoon ,  Hyunseok Lim ,  Jooyeon Ha

发明人： Joyoung Park ,  Hauk Han ,  Seok-Won Lee ,  Jeonggil Lee ,  Jinwoo Park ,  Kihyun Yoon ,  Hyunseok Lim ,  Jooyeon Ha

IPC分类号： H01L23/52 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

摘要： Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

公开(公告)号：US20170062472A1

公开(公告)日：2017-03-02

申请号：US15249590

申请日：2016-08-29

申请人： Joyoung PARK ,  HAUK HAN ,  SEOK-WON LEE ,  JEONGGIL LEE ,  JINWOO PARK ,  KlHYUN YOON ,  HYUNSEOK LIM ,  JOOYEON HA

发明人： Joyoung PARK ,  HAUK HAN ,  SEOK-WON LEE ,  JEONGGIL LEE ,  JINWOO PARK ,  KlHYUN YOON ,  HYUNSEOK LIM ,  JOOYEON HA

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

摘要： Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

摘要翻译： 公开了一种半导体存储器件，其包括在衬底上的堆叠，通过每个堆叠连接到衬底的垂直沟道部分以及布置在堆叠之间的分离图案。 每个堆叠可以包括堆叠在基板上的多个栅电极和插在栅电极之间的绝缘图案。 每个栅电极可以包括第一金属图案，其布置在绝缘图案之间以限定朝向垂直沟道部分凹陷的凹陷区域和设置在凹部区域中的第二金属图案。 第一和第二金属图案可以包含相同的金属材料，并且可以具有彼此不同的平均晶粒尺寸。

公开(公告)号：US09947684B2

公开(公告)日：2018-04-17

申请号：US15241781

申请日：2016-08-19

申请人： Joyoung Park ,  Yong-Hyun Kwon ,  Jeongsoo Kim ,  Seok-Won Lee ,  Jinwoo Park ,  Oik Kwon ,  Seungpil Chung

发明人： Joyoung Park ,  Yong-Hyun Kwon ,  Jeongsoo Kim ,  Seok-Won Lee ,  Jinwoo Park ,  Oik Kwon ,  Seungpil Chung

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L27/11568

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575

摘要： A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

公开(公告)号：US20160293539A1

公开(公告)日：2016-10-06

申请号：US15067833

申请日：2016-03-11

申请人： JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

发明人： JOYOUNG PARK ,  SEOK-WON LEE ,  SEONGJUN SEO

IPC分类号： H01L23/528 ,  H01L27/24 ,  H01L23/522 ,  H01L27/115

CPC分类号： H01L27/2481 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

摘要： A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

摘要翻译： 如下提供三维半导体器件。 基板包括接触区域，虚拟区域和单元阵列区域。 堆叠结构包括垂直堆叠在基板上的电极。 电极堆叠成在接触区域上具有第一分级结构，在虚拟区域中具有第二阶梯结构。 第二阶梯结构中的至少两个相邻电极的端部具有垂直对准的第一侧壁，使得第一侧壁的水平位置基本相同。

公开(公告)号：US20170200736A1

公开(公告)日：2017-07-13

申请号：US15349084

申请日：2016-11-11

申请人： Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

发明人： Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L27/11582 ,  H01L21/76879 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/0649

摘要： A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.