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    E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION
    1.
    发明申请
    E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION 有权
    具有自动钳位力调整和校准的电动自行车

    公开(公告)号：US20110042006A1

    公开(公告)日：2011-02-24

    申请号：US12938610

    申请日：2010-11-03

    申请人： Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

    发明人： Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

    IPC分类号： H01L21/46 ,  G06F19/00 ,  H01L21/465

    CPC分类号： H01L21/6831 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/909 ,  H01L2924/00

    摘要： The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.

    摘要翻译： 本公开描述了一种半导体制造装置。 该设备包括设计成对晶片执行处理的处理室; 配置在所述处理室中并设计成固定所述晶片的静电卡盘（E卡盘），其中所述E卡盘包括形成在所述电极上的电极和电介质特征; 调谐结构，其被设计成通过夹紧力将所述E卡盘保持在所述处理室中，其中所述调谐结构可操作以动态地调节所述夹紧力; 与E型卡盘集成并对夹紧力敏感的传感器; 以及过程控制模块，用于基于来自晶片的预测量数据和来自传感器的传感器数据来控制调谐结构以调整夹紧力。

    REAL-TIME CALIBRATION FOR WAFER PROCESSING CHAMBER LAMP MODULES
    5.
    发明申请
    REAL-TIME CALIBRATION FOR WAFER PROCESSING CHAMBER LAMP MODULES 有权
    用于加工室内灯模块的实时校准

    公开(公告)号：US20130306621A1

    公开(公告)日：2013-11-21

    申请号：US13471583

    申请日：2012-05-15

    申请人： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

    发明人： Chih-Tien Chang ,  Sunny Wu ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

    IPC分类号： H05B1/02

    CPC分类号： H01L22/26 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H05B1/0233

    摘要： An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.

    摘要翻译： 公开了一种装置，系统和方法。 示例性装置包括晶片处理室。 该设备还包括设置在不同区域中的辐射加热元件，其可操作以加热位于晶片处理室内的晶片的不同部分。 该装置还包括设置在晶片处理室外部的传感器，其可操作以监测来自设置在不同区域中的辐射加热元件的能量。 该装置还包括计算机，其被配置为利用传感器来表征设置在不同区域中的辐射加热元件，并且为放置在不同区域中的辐射加热元件提供校准，使得基本上均匀的温度分布保持在 晶圆。

    Physical Failure Analysis Guiding Methods
    9.
    发明申请
    Physical Failure Analysis Guiding Methods 有权
    物理故障分析指导方法

    公开(公告)号：US20110314336A1

    公开(公告)日：2011-12-22

    申请号：US12818003

    申请日：2010-06-17

    申请人： Sunny Wu ,  Yen-Di Tsen ,  Monghsung Chuang ,  Fu-Min Huang ,  Jo Fei Wang ,  Jong-I Mou

    发明人： Sunny Wu ,  Yen-Di Tsen ,  Monghsung Chuang ,  Fu-Min Huang ,  Jo Fei Wang ,  Jong-I Mou

    IPC分类号： G06F11/07

    CPC分类号： G01R31/2894

    摘要： A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

    摘要翻译： 一种方法包括提供多个故障管芯，并对多个故障管芯进行芯片探测以产生包括多个故障管芯的电气特性的数据记录。 执行自动网络跟踪以跟踪故障模块中的故障候选节点。 对从自动网络跟踪获得的结果执行故障层分析。 使用在执行故障层分析的步骤中获得的结果从多个故障模具中选择物理故障分析（PFA）样本。

    E-chuck for automated clamped force adjustment and calibration
    10.
    发明授权
    E-chuck for automated clamped force adjustment and calibration 有权
    用于自动夹紧力调节和校准的E型卡盘

    公开(公告)号：US07851233B2

    公开(公告)日：2010-12-14

    申请号：US12412138

    申请日：2009-03-26

    申请人： Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

    发明人： Jo Fei Wang ,  Sunny Wu ,  Jong-I Mou

    IPC分类号： H01L21/00

    CPC分类号： H01L21/6831 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/909 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.

    摘要翻译： 本发明提供一种半导体制造方法。 该方法包括对晶片执行第一处理; 在第一次处理之后测量晶片的晶片数据; 将晶片固定在处理室中的电子卡盘上; 从嵌入在E卡盘中的传感器收集传感器数据; 基于晶片数据和传感器数据调整到E卡盘的夹紧力; 然后对固定在处理室中的E型卡盘上的晶片进行第二处理。