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    Nitrided STI liner oxide for reduced corner device impact on vertical device performance
    1.
    发明授权
    Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
    氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响

    公开(公告)号：US06998666B2

    公开(公告)日：2006-02-14

    申请号：US10707754

    申请日：2004-01-09

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

    摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

    摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

    Pitcher-shaped active area for field effect transistor and method of forming same
    2.
    发明授权
    Pitcher-shaped active area for field effect transistor and method of forming same 失效
    投币型场效应晶体管及其形成方法

    公开(公告)号：US06960514B2

    公开(公告)日：2005-11-01

    申请号：US10803395

    申请日：2004-03-18

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

    摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

    NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE
    3.
    发明申请
    NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE 有权
    用于减少角膜器件的氮化硅氧化物对垂直器件性能的影响

    公开(公告)号：US20050151181A1

    公开(公告)日：2005-07-14

    申请号：US10707754

    申请日：2004-01-09

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

    摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

    摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

    Formation of self-aligned buried strap connector
    5.
    发明授权
    Formation of self-aligned buried strap connector 失效
    自对准埋地连接器的形成

    公开(公告)号：US06579759B1

    公开(公告)日：2003-06-17

    申请号：US10227396

    申请日：2002-08-23

    申请人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

    发明人： Michael Patrick Chudzik ,  Jochen Beintner ,  Ramachandra Divakaruni ,  Rajarao Jammy

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

    摘要： In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

    摘要翻译： 在垂直晶体管DRAM单元中，通过以下方式解决了深沟槽电容器的节点与垂直晶体管的下电极之间可靠的电连接的问题; 沉积临时绝缘体层，在临时绝缘体上方的沟槽壁上形成垂直间隔物，然后剥离绝缘体以露出衬底壁; 将掺杂剂扩散到衬底壁中以形成埋入带的自对准延伸部; 沉积最后的栅极绝缘体; 然后形成DRAM单元的上部。

    Structure and methods for process integration in vertical DRAM cell fabrication
    6.
    发明授权
    Structure and methods for process integration in vertical DRAM cell fabrication 有权
    垂直DRAM单元制造过程集成的结构和方法

    公开(公告)号：US06620676B2

    公开(公告)日：2003-09-16

    申请号：US09895672

    申请日：2001-06-29

    申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

    摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

    摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

    Trench isolation processes using polysilicon-assisted fill
    7.
    发明授权
    Trench isolation processes using polysilicon-assisted fill 有权
    使用多晶硅辅助填料的沟槽隔离工艺

    公开(公告)号：US06566228B1

    公开(公告)日：2003-05-20

    申请号：US10083744

    申请日：2002-02-26

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Jack A. Mandelman ,  Andreas Knorr

    IPC分类号： H01L2176

    CPC分类号： H01L21/76229 ,  H01L21/763 ,  H01L27/1052

    摘要： Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

    摘要翻译： 公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法，所述方法包括提供用于阵列和支撑区域的第一硬掩模层，所述第一硬掩模包括限定沟槽隔离的掩模开口 在阵列和支撑区域中，在阵列区域中提供深阵列沟槽隔离，在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层，通过所述第一硬 掩模材料下降到所述半导体衬底中，以便形成支撑沟槽隔离，使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度，并且其中包括一定数量的所述导电材料的导电元件保留在 每个所述深阵列沟槽。

    Structure and methods for process integration in vertical DRAM cell fabrication
    8.
    发明授权
    Structure and methods for process integration in vertical DRAM cell fabrication 有权
    垂直DRAM单元制造过程集成的结构和方法

    公开(公告)号：US06790739B2

    公开(公告)日：2004-09-14

    申请号：US10249997

    申请日：2003-05-27

    申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

    IPC分类号： H01L2120

    CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

    摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

    摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

    Method of making double-gated self-aligned finFET having gates of different lengths
    10.
    发明申请
    Method of making double-gated self-aligned finFET having gates of different lengths 失效
    制造具有不同长度的栅极的双门控自对准finFET的方法

    公开(公告)号：US20080176365A1

    公开(公告)日：2008-07-24

    申请号：US12077973

    申请日：2008-03-24

    申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

    发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

    摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

    摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。