公开(公告)号：US06905976B2

公开(公告)日：2005-06-14

申请号：US10249771

申请日：2003-05-06

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/302

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

公开(公告)号：US07129564B2

公开(公告)日：2006-10-31

申请号：US11059819

申请日：2005-02-17

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

IPC分类号： H01L31/117

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

公开(公告)号：US07101768B2

公开(公告)日：2006-09-05

申请号：US10260053

申请日：2002-09-27

申请人： Kenneth T. Settlemyer, Jr. ,  Porshia Shane Wrschka

发明人： Kenneth T. Settlemyer, Jr. ,  Porshia Shane Wrschka

IPC分类号： H01L21/20

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has at least an exposed layer of oxide and occupies only a “collar” portion of the sidewall, while a “capacitor” portion of the sidewall is free of the collar. A seeding layer is then selectively deposited on the capacitor portion of the sidewall. Then, hemispherical silicon grains are deposited on the seeding layer on the capacitor portion of the sidewall. A dielectric material is deposited, and then a conductor material, in that order, over the hemispherical silicon grains on the capacitor portion of the sidewall.

摘要翻译： 如本文所公开的，在集成电路中提供用于形成增强型电容沟槽电容器的方法。 该方法包括在半导体衬底中形成沟槽并在沟槽的侧壁上形成隔离环。 套环至少具有暴露的氧化物层，并且仅占据侧壁的“套环”部分，而侧壁的“电容器”部分没有套环。 然后在侧壁的电容器部分上选择性地沉积接种层。 然后，半球状硅晶粒沉积在侧壁的电容器部分上的接种层上。 然后依次将电介质材料沉积在侧壁的电容器部分上的半球形硅晶粒上。

公开(公告)号：US06905944B2

公开(公告)日：2005-06-14

申请号：US10249798

申请日：2003-05-08

申请人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

发明人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

IPC分类号： H01L21/76 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion. Finally, the lower portion of the trench is processed selectively to nitride, e.g. by one or more capacitor forming processes, and then the upper portion of the trench is processed.

摘要翻译： 通过本发明提供了蚀刻成半导体衬底的深沟槽的制造方法。 沟槽被分成上部和下部，并且该方法允许下部被加工成与上部不同。 在沟槽被蚀刻到半导体衬底中之后，在沟槽的侧壁上形成氮化物层。 然后在氮化物层上形成一层氧化物。 然后将填料材料沉积并凹入以覆盖沟槽下部的氧化物层，然后从填料材料上方的沟槽上部除去氧化物层。 一旦从沟槽的上部去除氧化物层，也可以去除填充材料，同时允许氧化物层和氮化物层保留在沟槽的下部。 选择性地将硅沉积在沟槽上部的暴露的氮化物层上。 然后从下部去除氧化物层和氮化物层。 最后，沟槽的下部被选择性地加工成氮化物，例如。 通过一个或多个电容器形成工艺，然后处理沟槽的上部。