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    Fine grain translation discrimination
    1.
    发明授权
    Fine grain translation discrimination 有权
    细粮翻译歧视

    公开(公告)号：US06363336B1

    公开(公告)日：2002-03-26

    申请号：US09417356

    申请日：1999-10-13

    申请人： John Banning ,  H. Peter Anvin ,  Benjamin Gribstad ,  David Keppel ,  Alex Klaiber ,  Paul Serris

    发明人： John Banning ,  H. Peter Anvin ,  Benjamin Gribstad ,  David Keppel ,  Alex Klaiber ,  Paul Serris

    IPC分类号： G06F900

    CPC分类号： G06F9/3812 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/45504 ,  G06F12/10

    摘要： A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.

    摘要翻译： 一种用于确定对存储器页面的写入是否被定向到已经被转换为将指令从目标指令集转换到主机指令集的计算机中的主机指令的目标指令的方法，包括以下步骤：检测对存储器页面的写入 将已经被转换为主机指令的目标指令存储在存储器页面中，检测写入的存储器页面的子区域是否存储已被翻译的目标指令，以及使从寻址的目标指令转换的主机指令无效。

    Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold
    2.
    发明授权
    Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold 有权
    当检测到存储器覆盖的频率超过阈值时，切换到可转换代码有效性的可修改代码的原始代码比较

    公开(公告)号：US07404181B1

    公开(公告)日：2008-07-22

    申请号：US11507779

    申请日：2006-08-21

    申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    IPC分类号： G06F9/455

    CPC分类号： G06F9/3808 ,  G06F9/3812

    摘要： A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

    摘要翻译： 将指令从目标指令集转换为主机指令集的方法。 在一个实施例中，多个第一目标指令被转换成多个第一主机指令。 在翻译之后，确定多个第一目标指令是否已改变。 如果确定减慢了计算机系统的操作，则存储第二多个目标指令的副本并与多个第一目标指令进行比较。 在比较之后，如果存在不匹配，则多个第一主机指令被无效。 根据一个实施例，当确定指示页面包含对多个第一目标指令的至少一个改变时，开始存储，比较和无效。 在一个实施例中，确定是通过检查与多个第一目标指令的存储器位置相关联的比特指示符。

    CONSISTENCY CHECKING FOR TRANSLATED INTRUCTIONS
    3.
    发明申请
    CONSISTENCY CHECKING FOR TRANSLATED INTRUCTIONS 有权
    一致性检查翻译内容

    公开(公告)号：US20120036502A1

    公开(公告)日：2012-02-09

    申请号：US13021609

    申请日：2011-02-04

    申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    IPC分类号： G06F9/455

    CPC分类号： G06F9/3808 ,  G06F9/3812

    摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

    摘要翻译： 在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。 响应于检测，将目标指令的副本存储在主机存储器中。 响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。 此外，响应于基于比较的不匹配，主机指令被禁用。

    SWITCHING TO ORIGINAL CODE COMPARISON OF MODIFIABLE CODE FOR TRANSLATED CODE VALIDITY WHEN FREQUENCY OF DETECTING MEMORY OVERWRITES EXCEEDS THRESHOLD
    7.
    发明申请
    SWITCHING TO ORIGINAL CODE COMPARISON OF MODIFIABLE CODE FOR TRANSLATED CODE VALIDITY WHEN FREQUENCY OF DETECTING MEMORY OVERWRITES EXCEEDS THRESHOLD 失效
    当检测到内存超过阈值的频率超过阈值时，切换到转换代码有效性的可修改代码的原始代码比较

    公开(公告)号：US20080313440A1

    公开(公告)日：2008-12-18

    申请号：US12177836

    申请日：2008-07-22

    申请人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    发明人： John Banning ,  H. Peter Anvin ,  Robert Bedicheck ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    IPC分类号： G06F9/315

    CPC分类号： G06F9/3808 ,  G06F9/3812

    摘要： A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

    摘要翻译： 将指令从目标指令集转换为主机指令集的方法。 在一个实施例中，多个第一目标指令被转换成多个第一主机指令。 在翻译之后，确定多个第一目标指令是否已改变。 如果确定减慢了计算机系统的操作，则存储第二多个目标指令的副本并与多个第一目标指令进行比较。 在比较之后，如果存在不匹配，则多个第一主机指令被无效。 根据一个实施例，当确定指示页面包含对多个第一目标指令的至少一个改变时，开始存储，比较和无效。 在一个实施例中，确定是通过检查与多个第一目标指令的存储器位置相关联的比特指示符。

    Translation consistency checking for modified target instructions by comparing to original copy
    8.
    发明授权
    Translation consistency checking for modified target instructions by comparing to original copy 有权
    通过与原始副本进行比较，对修改后的目标指令进行翻译一致性检查

    公开(公告)号：US06594821B1

    公开(公告)日：2003-07-15

    申请号：US09539987

    申请日：2000-03-30

    申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

    IPC分类号： G06F9455

    CPC分类号： G06F9/3808 ,  G06F9/3812

    摘要： A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.

    摘要翻译： 一种用于保持转换的主机指令与已经被转换了主机指令的目标指令之间的一致性的方法，包括维护已经进行转换的主机指令的目标指令的副本的步骤，将目标指令的副本与 在翻译时存储复制的目标指令的存储器地址处的目标指令，如果目标指令的副本与存储器地址处的目标指令不相同，则禁用转换的主机指令，并执行 如果目标指令的副本与存储器地址上的目标指令相同，则转换主机指令。

    Braided set associative caching techniques
    9.
    发明授权
    Braided set associative caching techniques 有权
    编织组合缓存技术

    公开(公告)号：US07725656B1

    公开(公告)日：2010-05-25

    申请号：US11583463

    申请日：2006-10-18

    申请人： Guillermo Rozas ,  Alexander Klaiber ,  Robert P. Masleid ,  John Banning ,  James Van Zoeren ,  Paul Serris

    发明人： Guillermo Rozas ,  Alexander Klaiber ,  Robert P. Masleid ,  John Banning ,  James Van Zoeren ,  Paul Serris

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0864

    摘要： A method and apparatus for storing and retrieving data in an N-way set associative cache with N data array banks is disclosed. On a cache fill corresponding to a particular way, a portion of each cache line (called a chunk) is placed in each data array bank. On a processor load seeking a requested chunk, a candidate chunk is retrieved from each data array bank and the requested chunk is selected from among the candidates.

    摘要翻译： 公开了一种用于在具有N个数据阵列组的N路组合关联高速缓存中存储和检索数据的方法和装置。 在对应于特定方式的缓存填充中，每个高速缓存行（称为块）的一部分被放置在每个数据阵列组中。 在寻求所请求的块的处理器负载上，从每个数据阵列库中检索候选块，并且从候选中选择所请求的块。

    Interpage prologue to protect virtual address mappings
    10.
    发明授权
    Interpage prologue to protect virtual address mappings 有权
    Interpage序言保护虚拟地址映射

    公开(公告)号：US06845353B1

    公开(公告)日：2005-01-18

    申请号：US09471447

    申请日：1999-12-23

    申请人： Robert Bedichek ,  David Keppel ,  John Banning

    发明人： Robert Bedichek ,  David Keppel ,  John Banning

    IPC分类号： G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F11/25 ,  G06F12/04

    CPC分类号： G06F9/3017

    摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

    摘要翻译： 在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址 目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。