公开(公告)号：US07716427B2

公开(公告)日：2010-05-11

申请号：US11969677

申请日：2008-01-04

申请人： John Barry Griswell, Jr. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

发明人： John Barry Griswell, Jr. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F9/38

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811

摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

摘要翻译： 在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。 预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。 预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。 预取引擎将预取队列中的条目与2M个连续高速缓存块的窗口进行比较。 当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。 当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

公开(公告)号：US20090070556A1

公开(公告)日：2009-03-12

申请号：US11969677

申请日：2008-01-04

申请人： John Barry Griswell, JR. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

发明人： John Barry Griswell, JR. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811

摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

摘要翻译： 在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。 预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。 预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。 预取引擎将预取队列中的条目与2M个连续高速缓存块的窗口进行比较。 当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。 当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

公开(公告)号：US07380066B2

公开(公告)日：2008-05-27

申请号：US11054871

申请日：2005-02-10

申请人： John Barry Griswell, Jr. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

发明人： John Barry Griswell, Jr. ,  Hung Qui Le ,  Francis Patrick O'Connell ,  William J. Starke ,  Jeffrey Adam Stuecheli ,  Albert Thomas Williams

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811

摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

摘要翻译： 在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。 预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。 预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。 预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。 当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。 当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

公开(公告)号：US07904661B2

公开(公告)日：2011-03-08

申请号：US11953637

申请日：2007-12-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07350029B2

公开(公告)日：2008-03-25

申请号：US11054889

申请日：2005-02-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07689775B2

公开(公告)日：2010-03-30

申请号：US12400052

申请日：2009-03-09

申请人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

发明人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/6024

摘要： Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system includes generating attribute information of prior data streams by associating attributes of each prior data stream with a storage access instruction which caused allocation of the data stream, and then recording the generated attribute information. The recorded attribute information is accessed, and a behavior of a new data stream is modified using the accessed recorded attribute information.

摘要翻译： 计算机实现方法，系统和计算机程序产品，用于在数据处理系统中预取数据。 一种用于在数据处理系统中预取数据的计算机实现方法包括通过将每个先前数据流的属性与导致数据流分配的存储访问指令相关联，然后记录所生成的属性信息来生成先前数据流的属性信息。 访问记录的属性信息，并且使用所访问的记录的属性信息来修改新的数据流的行为。

公开(公告)号：US20090164509A1

公开(公告)日：2009-06-25

申请号：US12400052

申请日：2009-03-09

申请人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

发明人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

IPC分类号： G06F12/00 ,  G06F17/30

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/6024

摘要： Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system includes generating attribute information of prior data streams by associating attributes of each prior data stream with a storage access instruction which caused allocation of the data stream, and then recording the generated attribute information. The recorded attribute information is accessed, and a behavior of a new data stream is modified using the accessed recorded attribute information.

摘要翻译： 计算机实现方法，系统和计算机程序产品，用于在数据处理系统中预取数据。 一种用于在数据处理系统中预取数据的计算机实现方法包括通过将每个先前数据流的属性与导致数据流分配的存储访问指令相关联，然后记录所生成的属性信息来生成先前数据流的属性信息。 访问记录的属性信息，并且使用所访问的记录的属性信息来修改新的数据流的行为。

公开(公告)号：US07516279B2

公开(公告)日：2009-04-07

申请号：US11364620

申请日：2006-02-28

申请人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

发明人： John Barry Griswell, Jr. ,  Francis Patrick O'Connell

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/6024

摘要： Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system includes generating attribute information of prior data streams by associating attributes of each prior data stream with a storage access instruction which caused allocation of the data stream, and then recording the generated attribute information. The recorded attribute information is accessed, and a behavior of a new data stream is modified using the accessed recorded attribute information.

摘要翻译： 计算机实现方法，系统和计算机程序产品，用于在数据处理系统中预取数据。 一种用于在数据处理系统中预取数据的计算机实现方法包括通过将每个先前数据流的属性与导致数据流分配的存储访问指令相关联，然后记录所生成的属性信息来生成先前数据流的属性信息。 访问记录的属性信息，并且使用所访问的记录的属性信息来修改新的数据流的行为。

公开(公告)号：US07669194B2

公开(公告)日：2010-02-23

申请号：US10926595

申请日：2004-08-26

申请人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  Allan Russell Martin ,  James Lawrence McInnes ,  Francis Patrick O'Connell

发明人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoqing Gao ,  Allan Russell Martin ,  James Lawrence McInnes ,  Francis Patrick O'Connell

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/4442

摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.

摘要翻译： 提供了一种通过使用集成高级和低级代码分析和优化的细粒度软件导向数据预取来最小化有效存储器延迟而不需要成本的机制。 该机制识别和分类流，识别最可能引起缓存未命中的数据，利用有效的硬件预取来确定要预取的流的适当数量，利用不同类型的流上的有效数据预取，以消除冗余预取和 避免高速缓存污染，并在指令调度程序中使用集成较低级别成本分析的高级转换，有效地调度预取指令。

公开(公告)号：US06915415B2

公开(公告)日：2005-07-05

申请号：US10042102

申请日：2002-01-07

申请人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

发明人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3455

摘要： A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

摘要翻译： 一种用于将微处理器系统中的一些软件预取指令映射到修改的硬件预取指令集并且通过调用相应的修改的硬件预取指令来执行软件预取的方法和装置。 对于常见的软件预取访问模式，通过将软件预取映射到硬件，可以实现改进的预取，而无需额外的硬件。