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公开(公告)号：US5109540A
公开(公告)日：1992-04-28
申请号：US701351
申请日：1991-05-10
申请人： John C. Dzung , Timothy A. Monahan-Mitchell , Emilio J. Quiroga , Craig F. Siddoway , Randall P. Chambers
发明人： John C. Dzung , Timothy A. Monahan-Mitchell , Emilio J. Quiroga , Craig F. Siddoway , Randall P. Chambers
IPC分类号： H04B1/38
CPC分类号： H04B1/3816 , H04B1/3883 , H04M1/0262
摘要： A portable two-way radio includes a radio portion and a battery removably attached to the radio portion. The radio portion includes an opening that is accessible when the battery is removed. An electronic card is received by the radio portion through the opening. When reassembled, the battery retains the electronic card in the radio portion.
摘要翻译： 便携式双向收音机包括无线电部分和可拆卸地附接到无线电部分的电池。 无线电部分包括当电池被移除时可接近的开口。 无线电部分通过开口接收电子卡。 重新组装时，电池将电子卡保存在收音机部分。
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公开(公告)号：US20080165753A1
公开(公告)日：2008-07-10
申请号：US11621420
申请日：2007-01-09
申请人： Emilio J. Quiroga
发明人： Emilio J. Quiroga
CPC分类号： H03L7/00
摘要： A digital clock generation circuit (200) and method of operation (400). A digital clock (202) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (202) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (202) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (202) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).
摘要翻译： 数字时钟产生电路（200）和操作方法（400）。 数字时钟（202）产生具有第一频率或第二频率的输出（220）。 时钟控制电路（204,206）选择性地设置数字时钟（202）以产生第一频率或第二频率。 多余脉冲计数器（212）确定由数字时钟（202）在第二频率产生的脉冲数，该频率在第一频率处将产生的脉冲数不同，如果时钟频率变为第二频率 没有发生 输出相位校正电路（230,232,212）响应于数字时钟（202）从产生第二频率变为产生第一频率而去除来自由输出（220）计数的输出（220）的脉冲数 过量脉冲计数器（212）。
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3.发明授权公开(公告)号：US07436919B2
公开(公告)日：2008-10-14
申请号：US11097577
申请日：2005-04-01
申请人： Mahibur Rahman , Emilio J. Quiroga
发明人： Mahibur Rahman , Emilio J. Quiroga
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , H04L7/04
摘要： Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.
摘要翻译： 提供方法，装置和系统用于将多个串行位流（106）与公共时钟信号（116）进行位同步。 对于与公共时钟信号的周期相对应的多个相位中的每一个，检测出每个比特流中发生的活动（304）。 基于在所选择的相位内检测到的活动，为每个串行比特流选择多个相位中的一个（308）。 然后使用公共时钟信号从针对每个串行比特流的所选择的相位提取数据（322），从而将多个串行比特流中的每一个相互同步。
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4.发明授权Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface 有权用于同步跨多针异步串行接口传输的数据的方法和装置公开(公告)号：US07936793B2
公开(公告)日：2011-05-03
申请号：US11097579
申请日：2005-04-01
申请人： Emilio J. Quiroga , Mahibur Rahman
发明人： Emilio J. Quiroga , Mahibur Rahman
CPC分类号： H04J3/0605 , H04J3/047 , H04L7/0338
摘要： Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams (106) with a serial framing signal (106A). Offset values (420) are determined (512) from the relative locations of predetermined data correlation values (107) stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (402), and the framing signal (106A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.
摘要翻译： 提供方法，装置和系统用于使串行成帧信号（106A）的多个串行数据比特流（106）进行字同步。 在相关模式期间从存储在数据缓冲器内的预定数据相关值（107）的相对位置确定偏移值（420）（512），以指示在成帧通道和每个串行数据通道之间观察到的偏斜量。 在每个数据流的后续操作期间接收的数据被存储在缓冲器（402）中，并且监视成帧信号（106A）以识别数据字之间的边界。 当发生帧边界时，使用先前存储的偏移值从缓冲器中提取并行数据，以补偿数据和成帧通道之间的位偏移。
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5.发明授权
公开(公告)号：US5949827A
公开(公告)日：1999-09-07
申请号：US934404
申请日：1997-09-19
CPC分类号： H04L25/061
摘要： A digital demodulator (100) for use in a communication device comprising a mixer (110) which samples a limited IF signal derived from a received radio frequency (RF) signal at a rate less than a Nyquist rate of the limited IF signal and generates a resulting IF signal. A continuous integrator (130) is connected to the mixer (110) and integrates the resulting IF signal over a predetermined number of samples thereof to generate a numerical value representative of a modulation frequency of a limited IF signal. An adaptive peak-valley bit slicer (150) is connected to the continuous integrator (130) and compares each numerical value with a peak threshold, a valley threshold and a mid threshold and generates most-significant-bit (MSB) and least-significant-bit (LSB) values for each sample. The adaptive peak-valley bit slicer (150) adjusts the peak and valley thresholds for use in determining a level of a current numerical value based on the LSB and MSB values determined for a prior sample of the numerical value.
摘要翻译： 一种用于通信设备的数字解调器（100），包括：混合器（110），其以小于受限IF信号的奈奎斯特速率的速率从接收到的射频（RF）信号中得到的有限IF信号进行采样， 产生IF信号。 连续积分器（130）连接到混频器（110），并将所得IF信号在预定数量的采样上积分，以产生表示有限IF信号的调制频率的数值。 自适应峰谷位限幅器（150）连接到连续积分器（130），并将每个数值与峰值阈值，谷值阈值和中间阈值进行比较，并产生最高有效位（MSB）和最小有效位 （LSB）值。 自适应峰谷位限幅器（150）基于为数值的先前样本确定的LSB和MSB值来调整用于确定当前数值的电平的峰谷阈值。
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公开(公告)号：US07782991B2
公开(公告)日：2010-08-24
申请号：US11621387
申请日：2007-01-09
CPC分类号： H04L7/0029 , H03H17/0628 , H03H17/0685
摘要： A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.
摘要翻译： 一种具有重采样滤波器（106）的多速率处理电路（100），用于接受以第一时钟速率采样的采样输入信号（104），并且对采样的输入信号进行滤波以去除高于第二时钟速率的频谱带宽的频谱分量。 采样的输入信号表示以与第一时钟速率有关的第二时钟速率更有效地处理的信号。 多速率处理电路（100）还具有离散时间处理器（108），其接收重采样滤波器输出（130）并且处理以第一时钟速率的两倍的整数倍的输出。 离散时间处理器（108）还进一步从处理中排除所选择的采样，以便以第二时钟速率的两倍的整数倍有效地执行重采样滤波器输出（130）的离散时间处理。
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公开(公告)号：US07756231B2
公开(公告)日：2010-07-13
申请号：US11621420
申请日：2007-01-09
申请人： Emilio J. Quiroga
发明人： Emilio J. Quiroga
CPC分类号： H03L7/00
摘要： A digital clock generation circuit (200) and method of operation (400). A digital clock (250) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (250) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (250) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (250) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).
摘要翻译： 数字时钟产生电路（200）和操作方法（400）。 数字时钟（250）产生具有第一频率或第二频率的输出（220）。 时钟控制电路（204,206）选择性地设置数字时钟（250）以产生第一频率或第二频率。 多余脉冲计数器（212）确定在第二频率下由数字时钟（250）产生的脉冲数量，其数量在第一频率上将产生的脉冲数不同，如果时钟频率变为第二频率 没有发生 输出相位校正电路（230,232,212）响应于数字时钟（250）从产生第二频率变为产生第一频率而去除来自输出（220）的脉冲数，其由 过量脉冲计数器（212）。
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公开(公告)号：US20080165907A1
公开(公告)日：2008-07-10
申请号：US11621387
申请日：2007-01-09
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H03H17/0628 , H03H17/0685
摘要： A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.
摘要翻译： 一种具有重采样滤波器（106）的多速率处理电路（100），用于接受以第一时钟速率采样的采样输入信号（104），并且对采样的输入信号进行滤波以去除高于第二时钟速率的频谱带宽的频谱分量。 采样的输入信号表示以与第一时钟速率有关的第二时钟速率更有效地处理的信号。 多速率处理电路（100）还具有离散时间处理器（108），其接收重采样滤波器输出（130）并且处理以第一时钟速率的两倍的整数倍的输出。 离散时间处理器（108）还进一步从处理中排除所选择的采样，以便以第二时钟速率的两倍的整数倍有效地执行重采样滤波器输出（130）的离散时间处理。
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