公开(公告)号：US06192492B1

公开(公告)日：2001-02-20

申请号：US09037468

申请日：1998-03-10

申请人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

发明人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

IPC分类号： H02H305

CPC分类号： G06F11/10 ,  G06F13/385

摘要： An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error-correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

摘要翻译： 公开了具有纠错和检测能力的具有ATA的驱动接口。 完全ATA向后兼容，此接口与当前ATA系统使用相同的物理电缆和连接器，采用与早期版本的ATA标准提供的总线驱动器相同或向后兼容的总线驱动器，并使用带有电缆信号转换的信号 比当前ATA设备目前看到的更快。 错误检测功能指示数据块何时在设备和主机之间传输错误; 纠错特征识别错误发送的字，并校正接口侧的这些字。 为了保持ATA向后兼容性，数据完整性检查功能在数据传输中不需要附加字，数据校正功能不需要新的数据传输协议或额外的数据传输开销。 还公开了接口电路和能够以40MB /秒传输数据的新的ATA兼容传输模式，本地总线适配器为磁盘驱动器支持的速率。 鉴于ATA电缆和连接器的物理限制，纠错和检测功能对于纠正在高速传输期间损坏的数据字特别有用; 然而，纠错和检测也可以独立于快速传输模式进行操作。 与完全向后兼容性相一致，配置有新的，快速的错误纠正接口的硬盘驱动器在插入到传统计算机系统提供的当前ATA适配器时是透明的。

公开(公告)号：US5784390A

公开(公告)日：1998-07-21

申请号：US491513

申请日：1995-06-19

申请人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

发明人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

IPC分类号： G06F11/10 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F11/10 ,  G06F13/385

摘要： An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

摘要翻译： 公开了具有纠错和检测能力的具有ATA的驱动接口。 完全ATA向后兼容，此接口与当前ATA系统使用相同的物理电缆和连接器，采用与早期版本的ATA标准提供的总线驱动器相同或向后兼容的总线驱动器，并使用带有电缆信号转换的信号 比当前ATA设备目前看到的更快。 错误检测功能指示数据块何时在设备和主机之间传输错误; 纠错特征识别错误发送的字，并校正接口侧的这些字。 为了保持ATA向后兼容性，数据完整性检查功能在数据传输中不需要附加字，数据校正功能不需要新的数据传输协议或额外的数据传输开销。 还公开了接口电路和能够以40MB /秒传输数据的新的ATA兼容传输模式，本地总线适配器为磁盘驱动器支持的速率。 鉴于ATA电缆和连接器的物理限制，纠错和检测功能对于纠正在高速传输期间损坏的数据字特别有用; 然而，纠错和检测也可以独立于快速传输模式进行操作。 与完全向后兼容性一致，配置有新的，快速的纠错接口的硬盘驱动器在插入到传统计算机系统提供的当前ATA适配器时是透明的。

公开(公告)号：US08014977B1

公开(公告)日：2011-09-06

申请号：US12051733

申请日：2008-03-19

申请人： John C. Masiewicz ,  Mohammad Wares Ali

发明人： John C. Masiewicz ,  Mohammad Wares Ali

IPC分类号： H04L1/24

CPC分类号： G06F1/3268 ,  G06F1/3221 ,  G11B20/10 ,  Y02D10/154

摘要： A method for determining an amplitude for signal transmission over an interconnect is disclosed. The method includes transmitting a first signal to a host over a transmission medium at a first transmission frequency according to a first speed negotiation process and receiving a second signal from the host at the first transmission frequency. The method also includes measuring a first voltage amplitude of the second signal and transmitting a third signal to the host at a second transmission frequency according to a second speed negotiation process. The method further includes receiving a fourth signal from the host at the second transmission frequency, measuring a second voltage amplitude of the fourth signal, and determining an approximate voltage loss in response to the first and second voltage amplitudes.

摘要翻译： 公开了一种用于确定互连上的信号传输的幅度的方法。 该方法包括根据第一速度协商过程以第一传输频率通过传输介质向主机发送第一信号，并以第一传输频率从主机接收第二信号。 该方法还包括测量第二信号的第一电压幅度，并根据第二速度协商过程以第二传输频率向主机发送第三信号。 该方法还包括以第二传输频率从主机接收第四信号，测量第四信号的第二电压幅度，以及响应于第一和第二电压幅度确定近似电压损耗。

公开(公告)号：US07647544B1

公开(公告)日：2010-01-12

申请号：US11284450

申请日：2005-11-22

申请人： John C. Masiewicz

发明人： John C. Masiewicz

IPC分类号： G11C29/00 ,  H03M13/00 ,  G11B5/02

CPC分类号： G11B20/1879 ,  G11B20/1833

摘要： A disk drive is disclosed comprising a disk, a buffer memory, and control circuitry operable to receive a write command from a host, wherein the write command comprises write data and a write data address. Write EDC data is generated in response to the write data and the write data address, wherein the write data and the write EDC data are stored in the buffer memory. The write data is read from the buffer memory, and write check data is generated in response to the write data and the write data address. The write EDC data is read from the buffer memory and compared to the write check data to detect a write error. If the write error is not detected, the write data is written to the disk without writing the write EDC data to the disk.

摘要翻译： 公开了一种磁盘驱动器，其包括盘，缓冲存储器和可操作以从主机接收写命令的控制电路，其中所述写命令包括写数据和写数据地址。 响应于写数据和写数据地址产生写EDC数据，其中写数据和写EDC数据被存储在缓冲存储器中。 从缓冲存储器读取写入数据，并响应于写入数据和写入数据地址产生写入检查数据。 从缓冲存储器读取写入的EDC数据，并与写入检查数据进行比较以检测写入错误。 如果未检测到写入错误，写入数据将写入磁盘，而不将写入的EDC数据写入磁盘。

公开(公告)号：US09530436B1

公开(公告)日：2016-12-27

申请号：US13162863

申请日：2011-06-17

申请人： John C. Masiewicz

发明人： John C. Masiewicz

IPC分类号： G06F12/00 ,  G11B5/02 ,  G11B5/012 ,  G06F3/06

CPC分类号： G11B5/02 ,  G06F3/0631 ,  G06F3/0676 ,  G06F3/0679 ,  G11B5/012

摘要： A data storage device comprising a storage media and a controller is disclosed. The controller is configured to receive a write command including a logical address and new data associated with the logical address, to write the new data to a new physical address on the storage media, and to remove old data associated with the logical address from an old physical address on the storage media, wherein the new physical address and the old physical address are different.

摘要翻译： 公开了一种包括存储介质和控制器的数据存储设备。 控制器被配置为接收包括与逻辑地址相关联的逻辑地址和新数据的写入命令，以将新数据写入存储介质上的新物理地址，并且从旧的逻辑地址移除与逻辑地址相关联的旧数据 存储介质上的物理地址，其中新的物理地址和旧的物理地址不同。

公开(公告)号：US07366641B1

公开(公告)日：2008-04-29

申请号：US11092119

申请日：2005-03-28

申请人： John C. Masiewicz ,  Mohammad Wares Ali

发明人： John C. Masiewicz ,  Mohammad Wares Ali

IPC分类号： G06F15/16

CPC分类号： G06F1/3268 ,  G06F1/3221 ,  G11B20/10 ,  Y02D10/154

摘要： A disk drive including a disk, a signal measurement circuit to measure amplitudes of signals received from the host, and a processor for controlling operations in the disk drive. The processor under the control of a program in conjunction with the signal measurement circuit: measures an amplitude of a signal from a host during a first speed negotiation process and determines if the amplitude of the signal from the host is above a pre-determined amplitude for the disk drive. If so, the processor commands the disk drive to transmit the signals to the host at the measured amplitude of the first speed negotiation process. However, if the amplitude is below the pre-determined amplitude for the disk drive, a second speed negotiation process is forced using a low frequency signal from the host and calculations are performed to determine appropriate transmit amplitudes for the interconnect.

摘要翻译： 包括磁盘的磁盘驱动器，用于测量从主机接收的信号的幅度的信号测量电路以及用于控制磁盘驱动器中的操作的处理器。 结合信号测量电路的程序控制下的处理器：在第一速度协商过程中测量来自主机的信号的幅度，并且确定来自主机的信号的幅度是否高于预定的幅度 磁盘驱动器。 如果是这样，则处理器命令磁盘驱动器以第一速度协商过程的测量幅度将信号发送到主机。 然而，如果振幅低于磁盘驱动器的预定幅度，则强制使用来自主机的低频信号进行第二速度协商处理，并执行计算以确定互连的适当发射幅度。

公开(公告)号：US07673075B1

公开(公告)日：2010-03-02

申请号：US11131036

申请日：2005-05-17

申请人： John C. Masiewicz

发明人： John C. Masiewicz

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/4286

摘要： A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication in accordance with the SATA format with the host. The serial interface during the transmission of primitives in a pass-through phase, inserts pass-through information to the host within or outside of a Frame Information Structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.

摘要翻译： 以串行高级技术附件（SATA）格式通信地耦合到主机的设备。 该设备包括用于控制设备中的操作的处理器和用于根据主机的SATA格式来控制串行通信的串行接口。 在直通阶段传输原语期间的串行接口，在帧信息结构（FIS）中或外部向主机插入传递信息。 如果主机未启用通配，则主机将忽略传递信息。 但是，如果主机是通过启用，主机会识别传递信息。

公开(公告)号：US07404013B1

公开(公告)日：2008-07-22

申请号：US11130944

申请日：2005-05-17

申请人： John C. Masiewicz

发明人： John C. Masiewicz

IPC分类号： G06F3/00

CPC分类号： G06F13/4295 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0674

摘要： A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication with the host in accordance with the SATA format. The serial interface, after the transmission of a continued primitive, inserts pass-through information to the host within or outside of a frame information structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.

摘要翻译： 以串行高级技术附件（SATA）格式通信地耦合到主机的设备。 该设备包括用于控制设备中的操作的处理器和用于根据SATA格式来控制与主机的串行通信的串行接口。 串行接口在传输一个连续的原语之后，在帧信息结构（FIS）内部或外部向主机插入传递信息。 如果主机未启用通配，则主机将忽略传递信息。 但是，如果主机是通过启用，主机会识别传递信息。

公开(公告)号：US08145452B1

公开(公告)日：2012-03-27

申请号：US13196613

申请日：2011-08-02

申请人： John C. Masiewicz ,  Mohammad Wares Ali

发明人： John C. Masiewicz ,  Mohammad Wares Ali

IPC分类号： H04L1/24

CPC分类号： G06F1/3268 ,  G06F1/3221 ,  G11B20/10 ,  Y02D10/154

摘要： A disk drive including a method for determining an amplitude for signal transmission over an interconnect is disclosed. The drive includes a processor that is coupled to a signal measurement circuit and is under the control of a program in conjunction with the signal measurement circuit to transmit a first signal to the host over a transmission medium at a first transmission frequency according to a first speed negotiation process, receive a second signal from the host at the first transmission frequency, determine a first voltage amplitude of the second signal, transmit a third signal to the host at a second transmission frequency according to a second speed negotiation process, receive a fourth signal from the host at the second transmission frequency, determine a second voltage amplitude of the fourth signal, and determine an approximate voltage loss in response to the first and second voltage amplitudes.

摘要翻译： 公开了一种包括用于确定互连上的信号传输的幅度的方法的磁盘驱动器。 驱动器包括耦合到信号测量电路的处理器，并且在与信号测量电路结合的程序的控制下，根据第一速度以第一传输频率通过传输介质向主机发送第一信号 协商过程，以第一传输频率从主机接收第二信号，确定第二信号的第一电压幅度，根据第二速度协商过程以第二传输频率向主机发送第三信号，接收第四信号 从第二传输频率的主机确定第四信号的第二电压幅度，并且响应于第一和第二电压幅度确定近似的电压损耗。

公开(公告)号：US07280302B1

公开(公告)日：2007-10-09

申请号：US11280046

申请日：2005-11-16

申请人： John C. Masiewicz

发明人： John C. Masiewicz

IPC分类号： G11B15/18 ,  G01R31/28 ,  G01D18/00

CPC分类号： G11B19/048 ,  G11B19/041

摘要： A disk drive is disclosed for connecting to a host, the host comprising loopback circuitry operable to loop a pattern received from the disk drive back to the disk drive. The disk drive comprises interface circuitry including a transmitter driver operable to transmit transmission signals at a transmission amplitude, and a receiver driver operable to receive reception signals. The transmitter driver is configured to transmit at an initial transmission amplitude, and a calibration pattern is transmitted to the host through the transmitter driver. The reception signals received by the receiver driver are monitored to detect a loopback pattern representing a loopback of the calibration pattern. The loopback pattern is processed to detect an error, and the transmission amplitude is adjusted in response to the error.

摘要翻译： 公开了一种用于连接到主机的磁盘驱动器，所述主机包括环回电路，其可操作以将从所述磁盘驱动器接收的模式循环回所述磁盘驱动器。 磁盘驱动器包括接口电路，该接口电路包括可以以传输幅度传输传输信号的发射机驱动器和可操作以接收接收信号的接收机驱动器。 发射机驱动器被配置为以初始发射幅度发射，并且通过发射机驱动器将校准模式发送到主机。 监视由接收器驱动器接收到的接收信号，以检测表示校准模式的环回的环回模式。 处理回送模式以检测错误，并且响应于错误来调整发送幅度。