公开(公告)号：US20070136714A1

公开(公告)日：2007-06-14

申请号：US11275076

申请日：2005-12-08

申请人： John Cohn ,  Jason Hibbeler ,  Gustavo Tellez

发明人： John Cohn ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Embodiments herein present a method, service, computer program product, etc. or performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

摘要翻译： 本文的实施例提供了一种方法，服务，计算机程序产品等，或为设计执行屈服感知IC路由。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。

公开(公告)号：US20060064661A1

公开(公告)日：2006-03-23

申请号：US10946677

申请日：2004-09-22

申请人： Michael Gray ,  Jason Hibbeler ,  Gustavo Tellez ,  Robert Walker

发明人： Michael Gray ,  Jason Hibbeler ,  Gustavo Tellez ,  Robert Walker

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068

摘要： A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.

公开(公告)号：US20050050500A1

公开(公告)日：2005-03-03

申请号：US10604962

申请日：2003-08-28

申请人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5068

摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

公开(公告)号：US20080059918A1

公开(公告)日：2008-03-06

申请号：US11854000

申请日：2007-09-12

申请人： Paul Bergeron ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Paul Bergeron ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

摘要翻译： 提供三维结构，其提高半导体器件中某些结构的制造成品率。 三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。 因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。 提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

公开(公告)号：US20050050501A1

公开(公告)日：2005-03-03

申请号：US10604963

申请日：2003-08-28

申请人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5068

摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

公开(公告)号：US20060085769A1

公开(公告)日：2006-04-20

申请号：US10711978

申请日：2004-10-18

申请人： Paul Bergeron ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Paul Bergeron ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

CPC分类号： G06F17/5068

摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

摘要翻译： 提供三维结构，其提高半导体器件中某些结构的制造成品率。 三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。 因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。 提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

公开(公告)号：US20050048677A1

公开(公告)日：2005-03-03

申请号：US10604987

申请日：2003-08-29

申请人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Robert Allen ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F17/50 ,  H01L21/00

CPC分类号： G06F17/5068

摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

摘要翻译： 本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。 本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。 然后，本发明在目标通孔上或附近绘制标记物形状。 标记形状仅在每个目标通孔的水平或垂直方向绘制。 接下来，本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。 在扩展期间，不同的标记形状将被扩展到不同的长度。 本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。 本发明在垂直于第一方向的方向上重复上述处理。 本发明还可以用于消除某些不希望的结构，例如堆叠的通孔，或者可以用于固定其它问题，例如通孔间距不足。 然后，根据优化器产生的输出，本发明将冗余通孔添加到集成电路设计中。

公开(公告)号：US20080104568A1

公开(公告)日：2008-05-01

申请号：US11966135

申请日：2007-12-28

申请人： Paul BERGERON ,  Jason Hibbeler ,  Gustavo Tellez

发明人： Paul BERGERON ,  Jason Hibbeler ,  Gustavo Tellez

IPC分类号： G06F17/50 ,  H01L23/52

CPC分类号： G06F17/5068

摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on a layer above the lower layer are formed on a more planar surface and thus are more likely to function properly. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

摘要翻译： 提供三维结构，其提高半导体器件中某些结构的制造成品率。 三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。 因此，构建在下层上方的层上的结构形成在更平坦的表面上，因此更有可能正常地起作用。 提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

公开(公告)号：US20070143728A1

公开(公告)日：2007-06-21

申请号：US11676185

申请日：2007-02-16

申请人： John Cohn ,  Jason Hibbeler ,  Anthony Stamper ,  Jed Rankin

发明人： John Cohn ,  Jason Hibbeler ,  Anthony Stamper ,  Jed Rankin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

摘要翻译： 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。

公开(公告)号：US20060265684A1

公开(公告)日：2006-11-23

申请号：US10908593

申请日：2005-05-18

申请人： Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

发明人： Markus Buehler ,  John Cohn ,  David Hathaway ,  Jason Hibbeler ,  Juergen Koehl

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068

摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

摘要翻译： 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用交替 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。