公开(公告)号：US06322934B1

公开(公告)日：2001-11-27

申请号：US09409115

申请日：1999-09-30

Applicant: John David Cuthbert ,  Feng Jin

Inventor： John David Cuthbert ,  Feng Jin

IPC: G03F900

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A method is for making an integrated circuit on a semiconductor wafer, where the integrated circuit includes circuit features having a desired, relatively small, critical dimension. The method preferably comprises the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. The designing step preferably includes determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method preferably includes steps of fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps. The present invention recognizes that the scaling factor is not a single number, but instead is a non-linear function which is also based upon the shift between exposure steps.

Abstract translation: 一种用于在半导体晶片上制造集成电路的方法，其中集成电路包括具有期望的，相对小的临界尺寸的电路特征。 该方法优选地包括以下步骤：设计包括具有临界尺寸的图案特征的掩模版，以形成相应的电路特征，基于由多个曝光步骤之间移动而定义的重叠区域，使得电路特征具有期望的，相对较小的， 关键维度。 设计步骤优选地包括确定缩放因子函数，用于将图案特征的临界尺度和向电路特征的期望临界尺度的偏移相关联，同时考虑到比例因子函数也是该偏移的函数。 该方法优选包括以下步骤：基于多个曝光步骤，制造掩模版并使用掩模版将集成电路制成在半导体晶片上。 本发明认识到缩放因子不是单个数字，而是基于曝光步骤之间的偏移的非线性函数。

公开(公告)号：US06248485B1

公开(公告)日：2001-06-19

申请号：US09356638

申请日：1999-07-19

Applicant: John David Cuthbert

Inventor： John David Cuthbert

IPC: G03F900

CPC classification number: G03F7/70625

Abstract: A method and controller for controlling a process and system for patterning a feature in a photoresist on a semiconductor wafer. The present invention characterizes various components (both individually and collectively) of an image transfer system, including the illumination source, lens and product reticle, with regard to dimensional errors introduced into the image transfer process by these components. The collective error data or information provided in accordance with the present invention may be communicated to the image transfer system to control the image transfer system and the image transfer process and to ensure that the actual dimension of features patterned in the photoresist are within acceptable dimensional limits for these features.

Abstract translation: 一种用于控制用于图案化半导体晶片上的光致抗蚀剂中的特征的工艺和系统的方法和控制器。 本发明的特征在于涉及通过这些部件引入到图像转印过程中的尺寸误差的包括照明源，透镜和产品掩模版的图像传送系统的各种组件（单独地和集体地）。 根据本发明提供的集体误差数据或信息可以被传送到图像传送系统以控制图像传输系统和图像传送过程，并且确保在光致抗蚀剂中图案化的特征的实际尺寸在可接受的尺寸限度内 对于这些功能。

公开(公告)号：US4050821A

公开(公告)日：1977-09-27

申请号：US726603

申请日：1976-09-27

Applicant: John David Cuthbert ,  David Farnham Munro

Inventor： John David Cuthbert ,  David Farnham Munro

IPC: G01B11/02 ,  G01B11/28 ,  G01N21/22

CPC classification number: G01B11/28 ,  G01B11/02

Abstract: Very rapid and accurate linewidth measurements in selected subregions of an LSI mask or wafer are made by means of a low-cost apparatus. The apparatus embodies the recognition that an accurate linewidth determination can be made for any particular feature among a variety of features in a repeated array by a calibrated and normalized measurement of the average light transmission or reflection of a subregion that includes the feature. In turn, the measurement is automatically converted to a linewidth reading by analog computing circuitry.

Abstract translation: 通过低成本设备制造在LSI掩模或晶片的选定子区域中的非常快速和准确的线宽测量。 该装置体现了通过对包括特征的子区域的平均光透射或反射的校准和归一化测量，可以对重复阵列中的各种特征中的任何特征进行精确线宽确定的认识。 反过来，测量由模拟计算电路自动转换为线宽读数。

公开(公告)号：US3944369A

公开(公告)日：1976-03-16

申请号：US473233

申请日：1974-05-24

Applicant: John David Cuthbert ,  Delmer Lee Fehrs ,  David Farnham Munro

Inventor： John David Cuthbert ,  Delmer Lee Fehrs ,  David Farnham Munro

IPC: G01N21/956 ,  G01B11/24

CPC classification number: G01N21/95607

Abstract: In an optical comparison inspection system a single beam from a scanning light source is split to produce a pair of synchronously scanning focused light beams. One of the beams is directed onto a reference, light affecting patterned workpiece and the other beam is directed onto a similar patterned workpiece to be inspected. Both workpieces are mounted in optically equivalent positions on a traverse table which has a direction of travel orthogonal to parallel planes containing the scanning light beams. Pattern differences are represented by differences in photodetected representations of the two light beams, which are intensity modulated by the patterned workpieces. By electronically gating preselected combinations of the two modulated signals with circuitry employing multiple threshold detection elements, a resultant signal is produced which enables allowable edge aberrations to be discriminated from unacceptable defects in the patterns. Suitable display of the resultant signal permits an operator to rapidly ascertain both the number and location of only unacceptable defects.

Abstract translation: 在光学比较检查系统中，来自扫描光源的单个光束被分割以产生一对同步扫描的聚焦光束。 一个光束被引导到参考光，影响图案化的工件的光，另一个光束被引导到待检查的类似的图案化工件上。 两个工件安装在横向工作台上的光学等效位置上，该横动台具有与包含扫描光束的平行平面垂直的行进方向。 图案差异由两个光束的光电检测表示的差异表示，两个光束被图案化工件强度调制。 通过使用多个阈值检测元件的电路将两个调制信号的预选组合电门选通，产生得到的信号，其使允许的边缘像差与图案中不可接受的缺陷区分开。 所得信号的适当显示允许操作者快速地确定仅有不可接受的缺陷的数量和位置。

公开(公告)号：US06168904A

公开(公告)日：2001-01-02

申请号：US08939422

申请日：1997-09-29

Applicant: John David Cuthbert ,  Chong-Cheng Fu

Inventor： John David Cuthbert ,  Chong-Cheng Fu

IPC: G03C500

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract translation: 通过涉及图案分解的光刻步骤描述了集成电路制造的改进方法。 期望的最终图案被分解成用于光致抗蚀剂成像的两个或更多个组件图案，导致图像保真度的改善。

公开(公告)号：US5780316A

公开(公告)日：1998-07-14

申请号：US879109

申请日：1997-06-19

Applicant: Hongzong Chew ,  John David Cuthbert ,  Hamlet Herring ,  John Louis Ryan ,  Robert Ching-I Sun ,  Thomas Michael Wolf ,  Daniel Mark Wroge

Inventor： Hongzong Chew ,  John David Cuthbert ,  Hamlet Herring ,  John Louis Ryan ,  Robert Ching-I Sun ,  Thomas Michael Wolf ,  Daniel Mark Wroge

IPC: H01L21/82 ,  G03F7/20 ,  H01L23/544 ,  H01L21/00

CPC classification number: G03F7/70625 ,  G03F7/70658 ,  H01L22/34

Abstract: Linewidth control features having integral transistors are disclosed. Optical and electrical measurements of the linewidth control feature and its associated transistor may be correlated thereby providing a method of improving production processes.

Abstract translation: 公开了具有整体晶体管的线宽控制特征。 可以将线宽控制特征及其相关联的晶体管的光学和电学测量相关联，从而提供改进生产工艺的方法。